URL https://opencores.org/ocsvn/smii/smii/trunk

Subversion Repositories smii

[/] [smii/] [trunk/] [rtl/] [verilog/] [smii.v] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 142...	Line 142...
`else`	`else`
`if ((state[10] \| state[5]) & (tx_cnt == 4'd0))`	`if ((state[10] \| state[5]) & (tx_cnt == 4'd0))`
`mtx_clk_tmp <= 1'b1;`	`mtx_clk_tmp <= 1'b1;`
`else if (state[2] \| state[7])`	`else if (state[2] \| state[7])`
`mtx_clk_tmp <= 1'b0;`	`mtx_clk_tmp <= 1'b0;`
`gbuf bufg1`	`assign #1 mtx_clk = mtx_clk_tmp;`
`(`
`.CLK(mtx_clk_tmp),`
`.GL(mtx_clk)`
`);`
`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`begin`	`begin`
`tx_data_reg <= 8'd0;`	`tx_data_reg <= 8'd0;`
`tx_data_reg_valid <= 1'b0;`	`tx_data_reg_valid <= 1'b0;`
Line 239...	Line 235...
`else`	`else`
`if ((state[1] \| state[6]) & (rx_cnt == 4'd0))`	`if ((state[1] \| state[6]) & (rx_cnt == 4'd0))`
`mrx_clk_tmp <= 1'b1;`	`mrx_clk_tmp <= 1'b1;`
`else if (state[3] \| state[8])`	`else if (state[3] \| state[8])`
`mrx_clk_tmp <= 1'b0;`	`mrx_clk_tmp <= 1'b0;`
`gbuf bufg2`	`assign #1 mrx_clk = mrx_clk_tmp;`
`(`
`.CLK(mrx_clk_tmp),`
`.GL(mrx_clk)`
`);`
`assign mcoll = mcrs & mtxen;`	`assign mcoll = mcrs & mtxen;`
`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`