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[/] [smii/] [trunk/] [rtl/] [verilog/] [smii_module_inst_1.v] - Diff between revs 3 and 7

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Rev 3 Rev 7
Line 17... Line 17... 
   .sync(sync),
 
   .sync(sync),
 
   .state(state),
 
   .state(state),
 
   .clk(eth_clk),
 
   .clk(eth_clk),
 
   .rst(wb_rst)
 
   .rst(wb_rst)
 
   );
 
   );
 
obufdff obufdff_sync2
 
 
 
  (
 
 
 
   .d(sync),
 
 
 
   .pad(sync_pad_o[2]),
 
 
 
   .clk(eth_clk),
 
 
 
   .rst(wb_rst)
 
 
 
   );
 
 
 
eth_top eth_top1
 
eth_top eth_top1
 
        (
 
        (
 
         .wb_clk_i(wb_clk),
 
         .wb_clk_i(wb_clk),
 
         .wb_rst_i(wb_rst),
 
         .wb_rst_i(wb_rst),
 
         .wb_dat_i(wbs_eth1_cfg_dat_i),
 
         .wb_dat_i(wbs_eth1_cfg_dat_i),
Line 94... Line 87... 
   .mcrs(m1crs),
 
   .mcrs(m1crs),
 
   .state(state),
 
   .state(state),
 
   .clk(eth_clk),
 
   .clk(eth_clk),
 
   .rst(wb_rst)
 
   .rst(wb_rst)
 
   );
 
   );
 
 
 
obufdff obufdff_sync1
 
 
 
  (
 
 
 
   .d(sync),
 
 
 
   .pad(eth_sync_pad_o[1]),
 
 
 
   .clk(eth_clk),
 
 
 
   .rst(wb_rst)
 
 
 
   );
 
obufdff obufdff_tx1
 
obufdff obufdff_tx1
 
  (
 
  (
 
   .d(tx[1]),
 
   .d(tx[1]),
 
   .pad(eth_tx_pad_o[1]),
 
   .pad(eth_tx_pad_o[1]),
 
   .clk(eth_clk),
 
   .clk(eth_clk),

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