URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [ram_wb/] [ram_wb.yaml] - Diff between revs 7 and 8

Rev 7	Rev 8
Line 4...	Line 4...
`version: b3`	`version: b3`
`license: LGPL`	`license: LGPL`
`licensefile:`	`licensefile:`
`author:`	`author:`
`authormail:`	`authormail:`
`vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb@655 rtl`	`vccmd:`
`toplevel: ram_wb_b3`	`toplevel: ram_wb_b3`

`interfaces:`	`interfaces:`
`:wb_ifc: SOCM_IFC`	`:wb_ifc: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
Line 56...	Line 56...
`defn: clk`	`defn: clk`
`:wb_rst_i: SOCM_PORT`	`:wb_rst_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: rst`	`defn: rst`

`hdlfiles:`	`static_parameters:`
`:ram_wb_b3: SOCM_HDL_FILE`	`:ram_wb_b3: SOCM_SPARAM`
`use_syn: true`	`dir: .`
`use_sim: true`	`path: ./ram_wb_b3.v.in`
`type: verilog`	`file_dst: ram_wb_b3.v`
`path: rtl/ram_wb_b3.v`	`parameters:`

	`:MEM_SIZE: SOCM_SENTRY`
	`token: TOK_MEM_SIZE`
	`type: integer`
	`visible: true`
	`editable: true`
	`default: 20`

	`:MEM_ADR_WIDTH: SOCM_SENTRY`
	`token: TOK_MEM_ADR_WIDTH`
	`type: integer`
	`visible: true`
	`editable: true`
	`default: 15`