| Line 188... |
Line 188... |
end
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end
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def ifc_declaration( ifc_spec, ifc_name, length )
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def ifc_declaration( ifc_spec, ifc_name, length )
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ifc_spec.ports.each do |port_name, port|
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ifc_spec.ports.each do |port_name, port|
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@decl_part << "signal #{ifc_name}_#{port_name.to_s} : "
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@decl_part << "signal #{ifc_name}_#{port_name.to_s} : "
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| Line 219... |
Line 222... |
dst_inst_sel = src_inst
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dst_inst_sel = src_inst
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src_ifc_sel = dst_ifc
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src_ifc_sel = dst_ifc
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dst_ifc_sel = src_ifc
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dst_ifc_sel = src_ifc
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end
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end
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# length == 0 means, that no
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# signal is assigned to this connection
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if length[ port_name ] > 0
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port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
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port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
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# combine all sources
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# combine all sources
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tmp = "#{port_tmp_name} <= "
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tmp = "#{port_tmp_name} <= "
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# loop over instances
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# loop over instances
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src_inst_sel.each_with_index do |(inst_name, inst), i|
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src_inst_sel.each_with_index do |(inst_name, inst), i|
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( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
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( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
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if port != nil
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tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ]
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tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ]
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tmp << "#{inst_name}_#{tmp_name}"
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tmp << "#{inst_name}_#{tmp_name}"
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tmp << " and \n" unless i == src_inst_sel.size-1
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tmp << " and \n" unless i == src_inst_sel.size-1
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end
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end
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end
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tmp << ";\n"
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tmp << ";\n"
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@asgn_part << tmp
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@asgn_part << tmp
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# assign to destination
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# assign to destination
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tmp = ""
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tmp = ""
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dst_inst_sel.each_with_index do |(inst_name, inst), i|
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dst_inst_sel.each_with_index do |(inst_name, inst), i|
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( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
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( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
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if port != nil
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tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}"
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tmp << "#{inst_name}_#{tmp_name} <= #{port_tmp_name}"
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tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1
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tmp << "( #{port[ :len ]}-1 downto 0 )" if port[ :len ] > 1
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tmp << ";\n"
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tmp << ";\n"
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end
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end
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end
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@asgn_part << tmp
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@asgn_part << tmp
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end
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end
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end
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| Line 255... |
Line 268... |
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# TODO: add sig list as argument (or interface list) for entity description
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# TODO: add sig list as argument (or interface list) for entity description
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def get_entity( soc, entity_name )
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def get_entity( soc, entity_name )
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entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n")
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add_toplevel_sig( soc, entity_name )
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entity_str = SOCMaker::conf[ :LIC ].split(/\n/).map{ |s| "-- "+s }.join("\n") + "\n"
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entity_str << "-- Auto-Generated by #{SOCMaker::conf[ :app_name ]} \n"
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entity_str << "-- Auto-Generated by #{SOCMaker::conf[ :app_name ]} \n"
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entity_str << "-- Date: #{Time.now}\n"
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entity_str << "-- Date: #{Time.now}\n"
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entity_str << SOCMaker::conf[ :vhdl_include ] + "\n"
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entity_str << SOCMaker::conf[ :vhdl_include ] + "\n"
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entity_str << "entity #{entity_name} is \n"
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entity_str << "entity #{entity_name} is \n"
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tmp = entity_port_str( soc )
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tmp = entity_port_str( soc )
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| Line 283... |
Line 297... |
entity_str << @inst_part
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entity_str << @inst_part
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entity_str << "end ARCHITECTURE IMPL;"
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entity_str << "end ARCHITECTURE IMPL;"
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return entity_str
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return entity_str
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end
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end
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def add_toplevel_sig( soc, entity_name )
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soc.ports do |port_name, length, dir, is_last|
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@asgn_part << "#{port_name} <= #{entity_name}_#{port_name}"
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@asgn_part << "," unless is_last
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@asgn_part << "\n"
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if length > 1
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@decl_part << "signal #{entity_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
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else
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@decl_part << "signal #{entity_name}_#{port_name} : std_logic;\n"
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end
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end
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end
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def asgn_str( ifc_spec, con, ifc_name, core1, core1_name, core2, core2_name )
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def asgn_str( ifc_spec, con, ifc_name, core1, core1_name, core2, core2_name )
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port_string = ""
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port_string = ""
|
