| Line 133... |
Line 133... |
# port_string
|
# port_string
|
#
|
#
|
def entity_port_str( core )
|
def entity_port_str( core )
|
port_string = ""
|
port_string = ""
|
|
|
core.ports do |port_name, port_dir, port_len, is_last |
|
core.ports do |port_name, port_dir, port_len, port_default, is_last |
|
|
|
# The string we are add in every iteration looks for example like
|
# The string we are add in every iteration looks for example like
|
# myportname1 : out std_logic_vector( 6-1 downto 0 )
|
# myportname1 : out std_logic_vector( 6-1 downto 0 )
|
# or
|
# or
|
# myportname2 : in std_logic
|
# myportname2 : in std_logic
|
#
|
#
|
port_string << port_name.to_s << " : "
|
port_string << port_name.to_s << " : "
|
|
|
puts port_name.to_s + ": dir: " + port_dir.to_s + ", len: " + port_len.to_s
|
|
|
|
|
|
# port direction
|
# port direction
|
if port_dir == 2
|
if port_dir == 2
|
port_string << " inout "
|
port_string << " inout "
|
| Line 184... |
Line 183... |
generic_str << "," unless is_last
|
generic_str << "," unless is_last
|
generic_str << "\n"
|
generic_str << "\n"
|
end
|
end
|
@inst_part << "generic map( \n#{generic_str} )\n" if generic_str.size > 0
|
@inst_part << "generic map( \n#{generic_str} )\n" if generic_str.size > 0
|
port_str = ""
|
port_str = ""
|
inst.ports do |port_name, dir, length, is_last|
|
inst.ports do |port_name, dir, length, default, is_last|
|
port_str << "#{port_name} => #{inst_name}_#{port_name}"
|
port_str << "#{port_name} => #{inst_name}_#{port_name}"
|
port_str << "," unless is_last
|
port_str << "," unless is_last
|
port_str << "\n"
|
port_str << "\n"
|
if length > 1
|
if length > 1
|
@decl_part << "signal #{inst_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
|
@decl_part << "signal #{inst_name}_#{port_name} : std_logic_vector( #{length}-1 downto 0 );\n"
|
| Line 198... |
Line 197... |
end
|
end
|
@inst_part << "port map( \n#{port_str} );\n\n\n" if port_str.size > 0
|
@inst_part << "port map( \n#{port_str} );\n\n\n" if port_str.size > 0
|
|
|
end
|
end
|
|
|
|
def add_ifc_default_assignment( inst, inst_name, ifc_name, default )
|
|
|
|
|
|
tmp = ""
|
|
inst.ports( ifc_name.to_s ) do |port_name, dir, length, default, is_last|
|
|
if dir == 1 # assign default value only if it is an input
|
|
if length > 1
|
|
tmp << "#{inst_name}_#{port_name} <= ( others => '#{default}' );\n"
|
|
else
|
|
tmp << "#{inst_name}_#{port_name} <= '#{default}';\n"
|
|
end
|
|
end
|
|
end
|
|
@asgn_part << tmp
|
|
|
|
end
|
|
|
def add_ifc_connection( ifc_spec, ifc_name, length, src_inst, dst_inst, src_ifc, dst_ifc )
|
def add_ifc_connection( ifc_spec, ifc_name, length, src_inst, dst_inst, src_ifc, dst_ifc )
|
|
|
###
|
###
|
#
|
#
|
# declaration
|
# declaration
|
| Line 224... |
Line 238... |
###
|
###
|
#
|
#
|
# assignment
|
# assignment
|
#
|
#
|
#
|
#
|
ifc_spec.ports.each do |port_name, port_dir|
|
ifc_spec.ports.each do |port_name, port_setup|
|
if port_dir == 0
|
|
|
|
|
if port_setup[ :dir ] == 0
|
src_inst_sel = src_inst
|
src_inst_sel = src_inst
|
dst_inst_sel = dst_inst
|
dst_inst_sel = dst_inst
|
src_ifc_sel = src_ifc
|
src_ifc_sel = src_ifc
|
dst_ifc_sel = dst_ifc
|
dst_ifc_sel = dst_ifc
|
else
|
else
|
| Line 247... |
Line 263... |
port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
|
port_tmp_name = "#{ifc_name}_#{port_name.to_s}"
|
|
|
|
|
# combine all sources
|
# combine all sources
|
tmp = "#{port_tmp_name} <= "
|
tmp = "#{port_tmp_name} <= "
|
assigned = false
|
|
|
|
# loop over instances
|
# loop over instances
|
src_inst_sel.each_with_index do |(inst_name, inst), i|
|
src_inst_sel.each_with_index do |(inst_name, inst), i|
|
( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
|
( tmp_name, port) = inst.get_port( src_ifc_sel[ inst_name ], port_name )
|
if port != nil
|
if port != nil
|
tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & " if port[ :len ] < length[ port_name ]
|
if port[ :len ] < length[ port_name ]
|
|
tmp << "\"" + "0" * ( length[ port_name ] - port[ :len ] ) + "\" & "
|
|
end
|
tmp << "#{inst_name}_#{tmp_name}"
|
tmp << "#{inst_name}_#{tmp_name}"
|
tmp << " and \n" unless i == src_inst_sel.size-1
|
tmp << " and \n" unless i == src_inst_sel.size-1
|
assigned = true
|
else
|
|
puts "#{port_tmp_name}: #{length[port_name] > 1}"
|
|
if length[ port_name ] > 1
|
|
tmp << "( others => '0' )"
|
|
else
|
|
tmp << "'0'"
|
|
end
|
end
|
end
|
end
|
end
|
tmp << ";\n"
|
tmp << ";\n"
|
@asgn_part << tmp if assigned
|
@asgn_part << tmp
|
|
|
|
|
puts src_inst_sel.size
|
|
puts tmp
|
|
|
|
|
|
tmp = ""
|
tmp = ""
|
assigned = false
|
assigned = false
|
# assign to destination
|
# assign to destination
|
dst_inst_sel.each_with_index do |(inst_name, inst), i|
|
dst_inst_sel.each_with_index do |(inst_name, inst), i|
|
| Line 282... |
Line 299... |
assigned = true
|
assigned = true
|
end
|
end
|
end
|
end
|
end
|
end
|
@asgn_part << tmp if assigned
|
@asgn_part << tmp if assigned
|
|
puts "NOT ASSIGNED DST" if not assigned
|
|
else
|
|
# puts "ifc #{ifc_name} port #{port_name.to_s} is not assigned"
|
|
# p src_ifc
|
|
# p dst_ifc
|
|
# tmp = ""
|
|
# dst_inst_sel.each_with_index do |(inst_name, inst), i|
|
|
# p inst_name
|
|
# p port_name
|
|
# ( tmp_name, port) = inst.get_port( dst_ifc_sel[ inst_name ], port_name )
|
|
# tmp << "#{inst_name}_#{tmp_name} <= ( others => 'X' );\n"
|
|
# end
|
|
# @asgn_part << tmp;
|
end
|
end
|
|
|
end
|
end
|
end
|
end
|
|
|
