URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [fpga/] [rtl/] [xml/] [Nexys2_fpga_padring.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 1...	Line 1...


`// //`	`// //`
`// Author : John Eaton Ouabache Designworks //`	`// Author : John Eaton Ouabache Designworks //`
`// //`	`// //`
`// Copyright (C) 2010 Authors and OPENCORES.ORG //`	`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
Line 38...	Line 38...
`fpga`	`fpga`
`padring default`	`padring default`









	`gen_verilog_pad`
	`104.0`
	`none`
	`pad`
	`./tools/verilog/gen_verilog`


	`destination`
	`top.fpga`







`gen_ise_filelist`	`gen_ise_filelist`
`104.0`	`104.0`
`none`	`none`

Line 1265...	Line 1286...









`gen_verilog_pad`
`104.0`
`none`
`pad`
`./tools/verilog/gen_verilog`


`destination`
`top.fpga`


`dest_dir`
`../verilog`












Line 1337...	Line 1339...
`CLOCK_PLL_DIV4`	`CLOCK_PLL_DIV4`
`CLOCK_PLL_SIZE4`	`CLOCK_PLL_SIZE4`
`CLOCK_SRC0`	`CLOCK_SRC0`
`RESET_SENSE0`	`RESET_SENSE0`
`CHIP_ID32'hf1c2e093`	`CHIP_ID32'hf1c2e093`
`WIDTH_11`
`WIDTH_22`
`WIDTH_33`
`WIDTH_44`
`WIDTH_77`
`WIDTH_88`
`WIDTH_1616`
`WIDTH_2323`
`WIDTH_4040`