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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [jtag/] [rtl/] [verilog/] [syn/] [jtag_tap.v] - Diff between revs 131 and 133

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Rev 131 Rev 133
Line 58... Line 58...
// want to attach multiple devices to the BSCAN device, which means
// want to attach multiple devices to the BSCAN device, which means
// you'll be making changes to this file anyway.
// you'll be making changes to this file anyway.
 
 
 
 
module cde_jtag_tap
module cde_jtag_tap
   #( parameter
#(parameter  CHIP_ID_VAL=32'h00000000 )
      JTAG_SEL=2
 
    )
 
 
 
(
(
 
 
input   wire [ 1:0 ]   tdo_i,
input   wire           tdo_i,
output  wire           shiftcapture_dr_clk_o,
output  wire           shiftcapture_dr_clk_o,
output  wire           tdi_o,
output  wire           tdi_o,
output  wire           test_logic_reset_o,
output  wire           test_logic_reset_o,
output  wire           shift_dr_o,
output  wire           shift_dr_o,
output  wire           capture_dr_o,
output  wire           capture_dr_o,
output  wire           update_dr_clk_o,
output  wire           update_dr_clk_o,
output  wire [ 1:0 ]   select_o
output  wire           select_o,
 
 
 
 
 
input   wire           aux_tdo_i,
 
output  wire           aux_shiftcapture_dr_clk_o,
 
output  wire           aux_tdi_o,
 
output  wire           aux_test_logic_reset_o,
 
output  wire           aux_shift_dr_o,
 
output  wire           aux_capture_dr_o,
 
output  wire           aux_update_dr_clk_o,
 
output  wire           aux_select_o
 
 
);
);
 
 
wire       update_dr_i;
wire       update_dr_i;
 
 
Line 84... Line 91...
BSCAN_SPARTAN3_inst (
BSCAN_SPARTAN3_inst (
   .CAPTURE (capture_dr_o),         // CAPTURE output from TAP controller
   .CAPTURE (capture_dr_o),         // CAPTURE output from TAP controller
   .DRCK1   (user1_clk_i),          // shiftcapture clk for USER1 functions
   .DRCK1   (user1_clk_i),          // shiftcapture clk for USER1 functions
   .DRCK2   (user2_clk_i),          // shiftcapture clk for USER2 functions
   .DRCK2   (user2_clk_i),          // shiftcapture clk for USER2 functions
   .RESET   (test_logic_reset_o),   // Reset output from TAP controller
   .RESET   (test_logic_reset_o),   // Reset output from TAP controller
   .SEL1    (select_o[0]),          // USER1 active output
   .SEL1    (select_o),             // USER1 active output
   .SEL2    (select_o[1]),          // USER2 active output
   .SEL2    (aux_select_o),         // USER2 active output
   .SHIFT   (shift_dr_o),           // SHIFT output from TAP controller
   .SHIFT   (shift_dr_o),           // SHIFT output from TAP controller
   .TDI     (tdi_o),                // TDI output from TAP controller
   .TDI     (tdi_o),                // TDI output from TAP controller
   .UPDATE  (update_dr_i),          // UPDATE output from TAP controller
   .UPDATE  (update_dr_i),          // UPDATE output from TAP controller
   .TDO1    (tdo_i[0]),             // Data input for USER1 function
   .TDO1    (tdo_i),                // Data input for USER1 function
   .TDO2    (tdo_i[1])              // Data input for USER2 function
   .TDO2    (aux_tdo_i)             // Data input for USER2 function
);
);
 
 
// Since we don't generate a update_clk we make one from the update state decode
// Since we don't generate a update_clk we make one from the update state decode
BUFG
BUFG
update_buf (
update_buf (
Line 102... Line 109...
   .I       (update_dr_i)             // Clock buffer input
   .I       (update_dr_i)             // Clock buffer input
            );
            );
 
 
 
 
BUFG
BUFG
 
aux_update_buf (
 
   .O       (aux_update_dr_clk_o),        // Clock buffer output
 
   .I       (update_dr_i)             // Clock buffer input
 
            );
 
 
 
 
 
 
 
 
 
 
 
BUFG
user1_clk_buf (
user1_clk_buf (
   .O       (shiftcapture_dr_clk_o),              // Clock buffer output
   .O       (shiftcapture_dr_clk_o),              // Clock buffer output
   .I       (user1_clk_i && user2_clk_i )             // Clock buffer input
   .I       (user1_clk_i && user2_clk_i )             // Clock buffer input
            );
            );
 
 
 
 
 
 BUFG
 
user2_clk_buf (
 
   .O       (aux_shiftcapture_dr_clk_o),              // Clock buffer output
 
   .I       (user1_clk_i && user2_clk_i )             // Clock buffer input
 
            );
 
 
 
 
 
 
 
assign     aux_tdi_o               = tdi_o;
 
assign     aux_test_logic_reset_o  = test_logic_reset_o ;
 
assign     aux_shift_dr_o          = shift_dr_o ;
 
assign     aux_capture_dr_o        = capture_dr_o;
 
 
 
 
 
 
endmodule
endmodule
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