URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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Rev 134 |
Line 23... |
Line 23... |
#( parameter
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#( parameter
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ADDR=10,
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ADDR=10,
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WIDTH=8,
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WIDTH=8,
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WORDS=1024,
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WORDS=1024,
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WRITETHRU=0,
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WRITETHRU=0,
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DEFAULT={WIDTH{1'b1}},
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INIT_FILE="NONE",
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INIT_FILE="NONE",
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MEM="NONE",
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MEM="NONE",
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INSTANCE_NAME="../../../../../children/")
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INSTANCE_NAME="../../../../../children/")
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(
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(
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input wire clk,
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input wire clk,
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Line 67... |
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always@(posedge clk) l_raddr <= addr;
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always@(posedge clk) l_raddr <= addr;
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// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
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// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
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wire [WIDTH-1:0] tmp_rdata;
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wire [WIDTH-1:0] tmp_rdata;
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assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
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assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
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always@(*) rdata = tmp_rdata;
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always@(*) rdata = tmp_rdata;
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end
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end
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else
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else
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begin
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begin
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// Read function gets old data if also a write cycle
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// Read function gets old data if also a write cycle
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always@(posedge clk)
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always@(posedge clk)
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if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];
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if( rd && cs ) rdata <= mem[{addr[ADDR-1:0]}];
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else rdata <= DEFAULT;
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else rdata <= {WIDTH{1'b1}};
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end
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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