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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [verilog/] [sram_dp.v] - Diff between revs 131 and 134

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Rev 131 Rev 134
Line 23... Line 23...
    #( parameter
    #( parameter
      ADDR=10,
      ADDR=10,
      WIDTH=8,
      WIDTH=8,
      WORDS=1024,
      WORDS=1024,
      WRITETHRU=0,
      WRITETHRU=0,
      DEFAULT={WIDTH{1'b1}},
 
      INIT_FILE="NONE",
      INIT_FILE="NONE",
      MEM="NONE",
      MEM="NONE",
      INSTANCE_NAME="../../../../../children/")
      INSTANCE_NAME="../../../../../children/")
     (
     (
 input   wire                 clk,
 input   wire                 clk,
Line 72... Line 71...
 
 
 
 
  always@(posedge clk)      l_raddr    <= raddr;
  always@(posedge clk)      l_raddr    <= raddr;
  // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
  // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
  wire  [WIDTH-1:0] tmp_rdata;
  wire  [WIDTH-1:0] tmp_rdata;
  assign                    tmp_rdata  =      (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:DEFAULT;
  assign                    tmp_rdata  =      (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
  always@(*)                rdata  =      tmp_rdata;
  always@(*)                rdata  =      tmp_rdata;
  end
  end
else
else
  begin
  begin
  // Read function gets old data if also a write cycle
  // Read function gets old data if also a write cycle
  always@(posedge clk)
  always@(posedge clk)
        if( rd && cs ) rdata             <= mem[{raddr[ADDR-1:0]}];
        if( rd && cs ) rdata             <= mem[{raddr[ADDR-1:0]}];
        else           rdata             <= DEFAULT;
        else           rdata             <= {WIDTH{1'b1}};
  end
  end
endgenerate
endgenerate
  endmodule
  endmodule
 
 
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