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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Diff between revs 134 and 135

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Rev 134	Rev 135
Line 1...	Line 1...



`-->`	`-->`

`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
`xmlns:socgen="http://digilentinc.com"`	`xmlns:socgen="http://digilentinc.com"`
`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`	`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`	`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`

`digilentinc.com`	`digilentinc.com`
`Nexys2`	`Nexys2`
`sram`	`sram`
`dp default`	`dp`


















`fs-sim`	`fs-sim`


`dest_dir../verilog/`	`dest_dir../verilog/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`








`fs-syn`	`fs-syn`



`dest_dir../verilog/`	`dest_dir../verilog/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`










`fs-lint`	`fs-lint`




`dest_dir../verilog/lint/`	`dest_dir../verilog/lint/`
`verilogSourcelibraryDir`	`verilogSourcelibraryDir`

























`sim:Simulation:`
`Verilog`	`verilog`
	`verilog`
`fs-sim`	`cde_sram_dp`


	`ADDR`
	`8`


	`WIDTH`
	`8`


	`WORDS`
	`256`


	`WRITETHRU`
	`1`



	`fs-sim`





`syn:Synthesis:`
`Verilog`

`fs-syn`




`lintlint`
`Verilog`

`fs-lint`







	`rtl`
	`verilog:Kactus2:`
	`verilog`



	`sim:Simulation:`
	`Verilog`

	`fs-sim`




	`syn:Synthesis:`
	`Verilog`

	`fs-syn`




	`lint:Lint:`
	`Verilog`

	`fs-lint`










`ADDR10`
`WIDTH8`
`WORDS1024`
`WRITETHRU0`







`clk`
`wire`
`in`


`cs`
`wire`
`in`


`wr`	`ADDR10`
`wire`	`WIDTH8`
`in`	`WORDS1024`
	`WRITETHRU0`


`rd`
`wire`
`in`



`waddr`
`wire`
`in`
`ADDR-10`


`raddr`	`clk`
`wire`	`wire`
`in`	`in`
`ADDR-10`


	`cs`
	`wire`
	`in`


`wdata`	`wr`
`wire`	`wire`
`in`	`in`
`WIDTH-10`


`rdata`	`rd`
`reg`	`wire`
`out`	`in`
`WIDTH-10`



	`waddr`
	`wire`
	`in`
	`ADDR-10`


	`raddr`
	`wire`
	`in`
	`ADDR-10`




	`wdata`
	`wire`
	`in`
	`WIDTH-10`


	`rdata`
	`reg`
	`out`
	`WIDTH-10`

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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Diff between revs 134 and 135