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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [componentCfg.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 149...	Line 149...









`default`	`default`

`CPU_ADD16`
`RAM_WORDS2048`	`RAM_WORDS2048`
`RAM_ADD11`	`RAM_ADD11`
`ROM_WORDS4096`	`ROM_WORDS4096`
`ROM_ADD12`	`ROM_ADD12`
`PROG_ROM_WORDS4096`	`PROG_ROM_WORDS4096`
`PROG_ROM_ADD12`	`PROG_ROM_ADD12`
	`CPU_ADD16`
`VEC_TABLE8'hff`	`VEC_TABLE8'hff`
`UART_PRESCALE5'b01100`	`UART_PRESCALE5'b01100`
`UART_PRE_SIZE5`	`UART_PRE_SIZE5`
`UART_DIV0`	`UART_DIV0`
`JTAG_SEL1`	`SPLIT_CH0_BITS8`
	`SPLIT_CH0_MATCH8'h00`
	`SPLIT_CH1_BITS4`
	`SPLIT_CH1_MATCH4'h0`
	`SPLIT_CH2_BITS8`
	`SPLIT_CH2_MATCH8'h80`
	`SPLIT_CH3_BITS4`
	`SPLIT_CH3_MATCH4'hc`
	`SPLIT_CH4_BITS4`
	`SPLIT_CH4_MATCH4'hf`
	`SPLIT_CH5_BITS4`
	`SPLIT_CH5_MATCH4'h4`







`ctrl_default`	`ctrl_default`

`VEC_TABLE8'hff`	`VEC_TABLE8'hff`

	`PG0_WIDTH8`
	`PG0_ADDR7`
	`PG0_WORDS128`
	`PG0_WRITETHRU0`
	`PG0_DEFAULT8'hff`







Line 190...	Line 214...



`T6502_def_tb`	`T6502_def_tb`
`def_tb`	`def_tb`
	`default`


	`UART_DIV0`
`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`



Line 221...	Line 246...



`T6502_def_vtb`	`T6502_def_vtb`
`def_vtb`	`def_vtb`
	`default`

`TIMEOUT1000`	`TIMEOUT1000`



Line 274...	Line 300...




`inst_1_test`	`inst_1_test`
	`default`
`T6502_def_vtb`	`T6502_def_vtb`

`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`ROM_FILE"opencores.org__Mos6502/sw/table/table.abs16"`	`ROM_FILE"opencores.org__Mos6502/sw/table/table.abs16"`
Line 292...	Line 319...




`kim_2`	`kim_2`
	`default`
`T6502_def_vtb`	`T6502_def_vtb`

`ROM_WORDS128`	`ROM_WORDS128`
`ROM_ADD7`	`ROM_ADD7`
`ROM_FILE"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`	`ROM_FILE"opencores.org__Mos6502/sw/table_tim1/table_tim1.abs16"`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [componentCfg.xml] - Diff between revs 131 and 133