URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [verilog/] [top.rtl] - Diff between revs 131 and 133

Rev 131	Rev 133
Line 12...	Line 12...
`assign pg00_ram_h_wr = (pg0_wr\|\|(mem_cs && mem_wr)) && ( pg0_add[0]);`	`assign pg00_ram_h_wr = (pg0_wr\|\|(mem_cs && mem_wr)) && ( pg0_add[0]);`
`assign io_module_pic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`	`assign io_module_pic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`
`assign io_module_vic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`	`assign io_module_vic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`


`cde_sram_dp`
`#( .WIDTH (8),`
`.ADDR (7),`
`.WORDS (128),`
`.DEFAULT (8'hff))`
`pg00_ram_l`
`(`
`.clk (clk),`
`.cs (1'b1),`
`.raddr (pg0_add[7:1]),`
`.rd (pg00_ram_rd),`
`.rdata (mem_rdata[7:0]),`
`.waddr (pg0_add[7:1]),`
`.wdata (mem_wdata[7:0]),`
`.wr (pg00_ram_l_wr));`
`cde_sram_dp`
`#( .WIDTH (8),`
`.ADDR (7),`
`.WORDS (128),`
`.DEFAULT (8'hff))`
`pg00_ram_h`
`(`
`.clk (clk),`
`.cs (1'b1),`
`.raddr (pg0_add[7:1]),`
`.rd (pg00_ram_rd),`
`.rdata (mem_rdata[15:8]),`
`.waddr (pg0_add[7:1]),`
`.wdata (mem_wdata[15:8]),`
`.wr (pg00_ram_h_wr));`


`//=============================================================================`	`//=============================================================================`
`//`	`//`
`//=============================================================================`	`//=============================================================================`