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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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Mos6502
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Mos6502
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T6502
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T6502
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ctrl default
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ctrl
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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T6502_ctrl
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T6502_ctrl
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fs-common
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fs-common
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../verilog/top.rtl
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../verilog/top.rtl
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verilogSourcefragment
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verilogSourcefragment
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fs-sim
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fs-sim
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../verilog/copyright.v
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../verilog/copyright.v
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verilogSourceinclude
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verilogSourceinclude
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../verilog/common/T6502_ctrl
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../verilog/common/T6502_ctrl
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verilogSourcemodule
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verilogSourcemodule
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fs-syn
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fs-syn
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../verilog/copyright.v
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../verilog/copyright.v
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verilogSourceinclude
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verilogSourceinclude
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../verilog/common/T6502_ctrl
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../verilog/common/T6502_ctrl
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verilogSourcemodule
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verilogSourcemodule
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Hierarchical
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Hierarchical
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Hierarchical
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Hierarchical
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spirit:library="Mos6502"
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spirit:name="T6502"
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spirit:version="ctrl.design"/>
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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logic_ctrl
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ipxact:library="Mos6502"
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ipxact:name="T6502"
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ipxact:version="logic_ctrl"/>
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commoncommon
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verilog
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Verilog
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fs-common
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-syn
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common:*common:*
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Verilog
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fs-common
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doc
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sim:*Simulation:*
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Verilog
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spirit:library="Testbench"
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fs-sim
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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syn:*Synthesis:*
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Verilog
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fs-syn
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doc
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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VEC_TABLE8'hff
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PG0_WIDTH8
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PG0_ADDR7
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PG0_WORDS128
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PG0_WRITETHRU0
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clk
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wire
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in
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cpu_pg0_data
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wire
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out70
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clk
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wire
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in
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pg00_ram_rd
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wire
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out
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pg00_ram_l_wr
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wire
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out
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pg00_ram_h_wr
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wire
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out
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mem_wdata
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wire
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in150
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mem_rdata
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wire
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out150
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pg0_add
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wire
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in71
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io_module_pic_irq_in
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wire
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out70
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io_module_vic_irq_in
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wire
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out70
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mem_rdata
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wire
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out150
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mem_wdata
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wire
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in150
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pg0_add
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wire
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in70
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mem_addr
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wire
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in00
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mem_cs
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wire
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in
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mem_wr
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wire
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in
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pg0_wr
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wire
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in
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mem_rd
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wire
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in
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pg0_rd
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wire
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in
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timer_irq
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wire
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in10
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rx_irq
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wire
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in
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tx_irq
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wire
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in
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ps2_data_avail
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wire
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in
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ext_irq_in
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wire
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in20
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