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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 39...	Line 39...
`T6502`	`T6502`
`ctrl default`	`ctrl default`






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`configuration`
`ctrl_default`


`dest_dir`
`io_ports`












`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.ctrl`	`T6502_ctrl`


`dest_dir`
`../verilog`





Line 121...	Line 90...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top.ctrl`	`../verilog/common/T6502_ctrl`
`verilogSourcemodule`	`verilogSourcemodule`




Line 140...	Line 109...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top.ctrl`	`../verilog/common/T6502_ctrl`
`verilogSourcemodule`	`verilogSourcemodule`




Line 240...	Line 209...



`VEC_TABLE8'hff`	`VEC_TABLE8'hff`



`PG0_WIDTH8`	`PG0_WIDTH8`
`PG0_ADDR7`	`PG0_ADDR7`

`PG0_WORDS128`	`PG0_WORDS128`

`PG0_WRITETHRU0`	`PG0_WRITETHRU0`


`PG0_DEFAULT8'hff`

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