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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Diff between revs 131 and 133

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Rev 131 Rev 133
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  elab_verilog
 
 
 
  103.0
 
 
 
  none
 
 
 
  :*Simulation:*
 
 
 
  ./tools/verilog/elab_verilog
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  trace_bus
 
 
 
  103.0
 
 
 
  none
 
 
 
  :*Simulation:*
 
 
 
  ./tools/verilog/trace_bus
 
 
 
    
 
 
    
 
 
      path
 
 
 
      root.dut.cpu
 
 
 
    
 
 
    
 
 
      bus_name
 
 
 
      cpu
 
 
 
    
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Line 81... Line 54... 
  none
 
  none
 
  common
 
  common
 
  ./tools/verilog/gen_verilog
 
  ./tools/verilog/gen_verilog
 
  
  
    
    
 
 
      configuration
 
 
 
      default
 
 
 
    
 
 
    
      destination
 
      destination
 
      tb.tb
 
      tb.tb
 
    
    
    
    
      dest_dir
 
      dest_dir

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