URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Show entire file |
Details |
Blame |
View Log
Rev 134 |
Rev 135 |
Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
Mos6502
|
Mos6502
|
T6502
|
T6502
|
def_vtb
|
def_vtb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
gen_verilog
|
104.0
|
104.0
|
none
|
none
|
common
|
:*common:*
|
./tools/verilog/gen_verilog
|
tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
tb.vtb
|
tb.vtb
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TIMEOUT10000
|
TIMEOUT10000
|
|
|
|
|
|
|
|
|
|
|
|
|
Params
|
Params
|
|
|
|
|
spirit:library="Mos6502"
|
ipxact:library="Mos6502"
|
spirit:name="T6502"
|
ipxact:name="T6502"
|
spirit:version="def_dut.params"/>
|
ipxact:version="def_dut.params"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilator
|
verilator
|
|
|
|
|
spirit:library="Testbench"
|
ipxact:library="Testbench"
|
spirit:name="toolflow"
|
ipxact:name="toolflow"
|
spirit:version="verilator"/>
|
ipxact:version="verilator"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
common:*common:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
syn:*Synthesis:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
lint:*Lint:*
|
lint:*Lint:*
|
Verilog
|
Verilog
|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
../verilog/sram.load
|
../verilog/sram.load
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
../verilog/tb.int_m
|
../verilog/tb.int_m
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
../verilog/top.vtb
|
../verilog/top.vtb
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
|
|
../verilog/common/tb.vtb
|
../verilog/common/tb.vtb
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
|
|
|
|
../verilog/common/tb.vtb
|
../verilog/common/tb.vtb
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.