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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [xml/] [core_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 110...	Line 110...







`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`









`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.sim`	`core_def`


`dest_dir`
`../verilog`





Line 156...	Line 133...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`core_def`


`dest_dir`
`../verilog`





Line 188...	Line 161...
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/sim/top.out.sim`	`../verilog/sim/core_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 273...	Line 246...





`../verilog/syn/top.out.syn`	`../verilog/syn/core_def`
`verilogSourcemodule`	`verilogSourcemodule`




Line 347...	Line 320...






`Hierarchical`

`spirit:library="Mos6502"`
`spirit:name="core"`
`spirit:version="def.design"/>`




`verilog`	`verilog`

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