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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 129... Line 129...
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      configuration
 
      default
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog_sim
  gen_verilog_sim
  104.0
  104.0
  none
  none
  :*Simulation:*
  :*Simulation:*
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
  
  
    
    
      destination
      destination
      top.out.sim
      cpu_def
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
Line 191... Line 161...
    
    
      fs-sim
      fs-sim
 
 
      
      
        
        
        ../verilog/sim/top.out.sim
        ../verilog/sim/cpu_def
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
      
      
Line 213... Line 183...
    
    
      fs-syn
      fs-syn
 
 
      
      
        
        
        ../verilog/sim/top.out.sim
        ../verilog/sim/cpu_def
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
      
      
Line 307... Line 277...
 BOOT_VEC8'hfc
 BOOT_VEC8'hfc
 CPU_ADD16
 CPU_ADD16
 PROG_ROM_ADD0
 PROG_ROM_ADD0
 PROG_ROM_WORDS0
 PROG_ROM_WORDS0
 PROG_ROM_WIDTH16
 PROG_ROM_WIDTH16
 PROG_ROM_DEFAULT16'hffff
 
 
 
 
 
 STACK_RAM_SIZE8
 STACK_RAM_SIZE8
 STACK_RAM_WORDS256
 STACK_RAM_WORDS256
 STACK_RAM_WIDTH16
 STACK_RAM_WIDTH16
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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