OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_lint.xml] - Diff between revs 131 and 133

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 131 Rev 133
Line 39... Line 39...
cpu
cpu
def_lint
def_lint
 
 
 
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
>
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      configuration
 
      default
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
  gen_design
 
  102.1
 
  none
 
  :*Simulation:*
 
>
 
  ./tools/verilog/gen_design
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.