URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.cpu1] - Diff between revs 131 and 133

Rev 131	Rev 133
Line 3...	Line 3...
`assign cpu1_ack_i = cpu1_stb_o;`	`assign cpu1_ack_i = cpu1_stb_o;`
`assign cpu1_data_i = 32'h23456789;assign tck_i = jtag_clk;`	`assign cpu1_data_i = 32'h23456789;assign tck_i = jtag_clk;`
`assign capture_dr_i = capture_dr_o;`	`assign capture_dr_i = capture_dr_o;`
`assign shift_dr_i = shift_dr_o;`	`assign shift_dr_i = shift_dr_o;`
`assign update_dr_i = update_dr_o;`	`assign update_dr_i = update_dr_o;`
`assign debug_select_i = select_o[0];`	`assign debug_select_i = select_o;`
`assign rst_i = test_logic_reset_o;`	`assign rst_i = test_logic_reset_o;`
`assign tdo_i[0] = tdo_o;`	`assign tdo_i = tdo_o;`
`assign tdo_i[1] = 1'b0;`
`assign bsr_tdo_i = 1'b0;`	`assign bsr_tdo_i = 1'b0;`
`assign tdi_i = tdi_o;`	`assign tdi_i = tdi_o;`