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https://opencores.org/ocsvn/socgen/socgen/trunk
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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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fpgas
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fpgas
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Nexys2_T6502
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Nexys2_T6502
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core default
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core
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gen_verilog
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gen_verilog
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104.0
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104.0
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none
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none
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common
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:*common:*
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./tools/verilog/gen_verilog
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tools/verilog/gen_verilog
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destination
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destination
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Nexys2_T6502_core
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Nexys2_T6502_core
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Hierarchical:*Simulation:*
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spirit:library="fpgas"
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spirit:name="Nexys2_T6502"
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spirit:version="core.design"/>
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Hierarchical
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Core:*Simulation:*
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spirit:library="Nexys2"
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spirit:name="fpga"
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spirit:version="core"/>
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Hierarchical:*Simulation:*
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Hierarchical
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verilog:*Simulation:*
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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Core:*Simulation:*
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ipxact:library="Nexys2"
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ipxact:name="fpga"
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ipxact:version="core"/>
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commoncommon
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verilog:*Simulation:*
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Verilog
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ipxact:library="Testbench"
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fs-common
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-sim
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common:*common:*
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Verilog
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-sim
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fs-common
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../verilog/top.jabc
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verilogSourcefragment
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../verilog/top.gpio
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verilogSourcefragment
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fs-common
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../verilog/top.rs_uart
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../verilog/top.jabc
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verilogSourcefragment
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verilogSourcefragment
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../verilog
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verilogSourcelibraryDir
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../verilog/top.gpio
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verilogSourcefragment
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../verilog/top.rs_uart
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verilogSourcefragment
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fs-sim
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../verilog
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verilogSourcelibraryDir
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/Nexys2_T6502_core
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verilogSourcemodule
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fs-sim
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/Nexys2_T6502_core
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verilogSourcemodule
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