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URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 43...	Line 43...







	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`configuration`
	`core`


	`dest_dir`
	`io_ports`







`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
Line 212...	Line 233...

`fs-sim`	`fs-sim`












`RAM_WORDS2048`
`RAM_ADD11`
`ROM_WORDS4096`
`ROM_ADD12`
`PROG_ROM_WORDSROM_WORDS`
`PROG_ROM_ADDROM_ADD`
`VEC_TABLE8'hff`
`UART_PRESCALE5'b01100`
`UART_PRE_SIZE5`
`UART_DIV0`
`JTAG_SEL1`
`JTAG_USER1_WIDTH8`
`JTAG_USER1_RESET8'h12`

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