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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 44... Line 44...
 
 
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      configuration
 
      core
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
Line 73... Line 56...
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
  
  
    
    
      destination
      destination
      top.T6502
      Nexys2_T6502_core
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
Line 95... Line 74...
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
 
 
      
 
        
 
        ../verilog/top.jabc
 
        verilogSourcefragment
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/top.gpio
 
        verilogSourcefragment
 
      
 
 
 
 
 
 
 
      
 
        
 
        ../verilog/top.rs_uart
 
        verilogSourcefragment
 
      
 
 
 
      
 
        ../verilog
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
   
 
 
 
 
 
   
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/top.T6502
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
 
 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
       
 
 
              
              
              Hierarchical
              Hierarchical:*Simulation:*
 
 
              
              
                                   spirit:library="fpgas"
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="core.design"/>
                                   spirit:version="core.design"/>
              
              
 
 
 
 
              
              
              Core
              Core:*Simulation:*
 
 
              
              
              
              
                                   spirit:library="Nexys2"
                                   spirit:library="Nexys2"
                                   spirit:name="fpga"
                                   spirit:name="fpga"
                                   spirit:version="core"/>
                                   spirit:version="core"/>
Line 192... Line 104...
 
 
              
              
 
 
 
 
              
              
              verilog
              verilog:*Simulation:*
              
              
              
              
                                   spirit:library="Testbench"
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
                                   spirit:version="verilog"/>
Line 237... Line 149...
 
 
      
      
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   
 
      fs-common
 
 
 
 
 
      
 
        
 
        ../verilog/top.jabc
 
        verilogSourcefragment
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/top.gpio
 
        verilogSourcefragment
 
      
 
 
 
 
 
 
 
      
 
        
 
        ../verilog/top.rs_uart
 
        verilogSourcefragment
 
      
 
 
 
      
 
        ../verilog
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
   
 
 
 
 
 
   
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
      
 
        
 
        ../verilog/common/Nexys2_T6502_core
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
 
 
 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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