OpenCores

URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Diff between revs 131 and 133

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 131	Rev 133
Line 36...	Line 36...
`opencores.org`	`opencores.org`
`fpgas`	`fpgas`
`Nexys2_T6502`	`Nexys2_T6502`
`default default`	`default default`












	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`configuration`
	`default`


	`dest_dir`
	`io_ports`







`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`configuration`
`default`


`destination`	`destination`
`top.T6502_default`	`top.T6502_default`


`dest_dir`	`dest_dir`
`../verilog`	`../verilog`



















`fs-sim`	`fs-sim`



Line 101...	Line 97...
`verilogSourcemodule`	`verilogSourcemodule`




















`Hierarchical`	`Hierarchical`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.