URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 38...	Line 38...
`Nexys2_T6502`	`Nexys2_T6502`
`default default`	`default default`




`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`configuration`
`default`


`dest_dir`
`io_ports`







`gen_verilog`	`gen_verilog`
Line 67...	Line 51...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.T6502_default`	`Nexys2_T6502_default`


`dest_dir`
`../verilog`









`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/common/top.T6502_default`
`verilogSourcemodule`











`Hierarchical`	`Hierarchical:Simulation:`


`spirit:library="fpgas"`	`spirit:library="fpgas"`
`spirit:name="Nexys2_T6502"`	`spirit:name="Nexys2_T6502"`
`spirit:version="fpga.design"/>`	`spirit:version="fpga.design"/>`



`Pad_Ring`	`Pad_Ring:Simulation:`



`spirit:library="Nexys2"`	`spirit:library="Nexys2"`
`spirit:name="fpga"`	`spirit:name="fpga"`
`spirit:version="jtag_padring"/>`	`spirit:version="jtag_padring"/>`




`verilog`	`verilog:Simulation:`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="verilog"/>`	`spirit:version="verilog"/>`










`commoncommon`	`commoncommon`
`Verilog`	`Verilog`

`fs-common`	`fs-common`
Line 167...	Line 123...





`doc`	`doc:Simulation:`


`spirit:library="Testbench"`	`spirit:library="Testbench"`
`spirit:name="toolflow"`	`spirit:name="toolflow"`
`spirit:version="documentation"/>`	`spirit:version="documentation"/>`
Line 179...	Line 135...
`:Documentation:`	`:Documentation:`
`Verilog`	`Verilog`










Line 192...	Line 146...








	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/Nexys2_T6502_default`
	`verilogSourcemodule`



	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`








	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/common/Nexys2_T6502_default`
	`verilogSourcemodule`



	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`









	`fs-lint`


	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Diff between revs 133 and 134