URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [verilog/] [tb.ext] - Diff between revs 131 and 133

Rev 131	Rev 133
Line 18...	Line 18...
`pullup pu_memdb_13 ( MEMDB[13] );`	`pullup pu_memdb_13 ( MEMDB[13] );`
`pullup pu_memdb_14 ( MEMDB[14] );`	`pullup pu_memdb_14 ( MEMDB[14] );`
`pullup pu_memdb_15 ( MEMDB[15] );`	`pullup pu_memdb_15 ( MEMDB[15] );`
`pullup pu_flashststs ( FLASHSTSTS );`	`pullup pu_flashststs ( FLASHSTSTS );`

`mt45w8mw12_def`
`psram (`
`.clk ( RAMCLK ),`
`.adv_n ( RAMADV ),`
`.cre ( RAMCRE ),`
`.o_wait ( RAMWAIT ),`
`.ce_n ( RAMCS ),`
`.oe_n ( MEMOE ),`
`.we_n ( MEMWR ),`
`.lb_n ( RAMLB ),`
`.ub_n ( RAMUB ),`
`.addr ( MEMADR ),`
`.dq ( MEMDB )`
`);`


`pullup pu_jtag ( JTAG_TDO );`	`pullup pu_jtag ( JTAG_TDO );`

`pullup pu_jtag ( PS2C );`	`pullup pu_jtag ( PS2C );`
`pullup pu_jtag ( PS2D );`	`pullup pu_jtag ( PS2D );`


`reg [7:0] SW_reg;`	`reg [7:0] SW_reg;`
	`reg [3:0] BTN_reg;`

`initial`	`initial`
`begin`	`begin`
`SW_reg = 8'h00;`	`SW_reg = 8'h00;`
	`BTN_reg = 4'h0;`
`end`	`end`

`assign SW = SW_reg;`	`assign SW = SW_reg;`
	`assign BTN = BTN_reg;`


`assign STOP = 1'b0;`	`assign STOP = 1'b0;`
`assign BAD = 1'b0;`	`assign BAD = 1'b0;`