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https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// ./tools/verilog/gen_tb -vendor opencores.org -library fpgas -component Nexys2_T6502 -version default //
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// ./tools/verilog/gen_tb -vendor opencores.org -library fpgas -component Nexys2_T6502 -version default //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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fpgas
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fpgas
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Nexys2_T6502
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Nexys2_T6502
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default_duth.design
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default_duth.design
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AN
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AN
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A_CLK
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A_CLK
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BTN
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BTN
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B_CLK
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B_CLK
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CTS
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CTS
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DP
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DP
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EPPASTB
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EPPASTB
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EPPDB
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EPPDB
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EPPDSTB
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EPPDSTB
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EPPWAIT
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EPPWAIT
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FLASHCS
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FLASHCS
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FLASHRP
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FLASHRP
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FLASHSTSTS
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FLASHSTSTS
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HSYNC_N
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HSYNC_N
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JA_10
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JA_10
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JA_1
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JA_1
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JA_2
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JA_2
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JA_3
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JA_3
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JA_4
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JA_4
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JA_7
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JA_7
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JA_8
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JA_8
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JA_9
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JA_9
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JB_10
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JB_10
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JB_1
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JB_1
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JB_2
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JB_2
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JB_3
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JB_3
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JB_4
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JB_4
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JB_7
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JB_7
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JB_8
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JB_8
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JB_9
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JB_9
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JC_10
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JC_10
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JC_1
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JC_1
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JC_2
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JC_2
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JC_3
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JC_3
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JC_4
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JC_4
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JC_7
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JC_7
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JC_8
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JC_8
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JC_9
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JC_9
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JTAG_TCK
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JTAG_TCK
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JTAG_TDI
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JTAG_TDI
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JTAG_TDO
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JTAG_TDO
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JTAG_TMS
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JTAG_TMS
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JTAG_TRESET_N
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JTAG_TRESET_N
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LED
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LED
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MEMADR
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MEMADR
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MEMDB
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MEMDB
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MEMOE
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MEMOE
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MEMWR
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MEMWR
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PIO
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PIO
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PS2C
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PS2C
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PS2D
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PS2D
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RAMADV
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RAMADV
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RAMCLK
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RAMCLK
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RAMCRE
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RAMCRE
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RAMCS
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RAMCS
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RAMLB
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RAMLB
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RAMUB
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RAMUB
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RAMWAIT
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RAMWAIT
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RS_RX
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RS_RX
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RS_TX
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RS_TX
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RTS
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RTS
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RXD
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RXD
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SEG
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SEG
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SW
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SW
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TXD
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TXD
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USBADR
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USBADR
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USBCLK
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USBCLK
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USBDIR
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USBDIR
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USBFLAG
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USBFLAG
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USBMODE
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USBMODE
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USBOE
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USBOE
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USBPKTEND
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USBPKTEND
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USBRDY
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USBRDY
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USBWR
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USBWR
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VGABLUE
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VGABLUE
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VGAGREEN
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VGAGREEN
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VGARED
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VGARED
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VSYNC_N
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VSYNC_N
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dut
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dut
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CLOCK_FREQ
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CLOCK_FREQ
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CLOCK_PLL_DIV
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CLOCK_PLL_DIV
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CLOCK_PLL_MULT
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CLOCK_PLL_MULT
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CLOCK_PLL_SIZE
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CLOCK_PLL_SIZE
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CLOCK_SRC
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CLOCK_SRC
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JTAG_USER1_RESET
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JTAG_USER1_RESET
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JTAG_USER1_WIDTH
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JTAG_USER1_WIDTH
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PROG_ROM_ADD
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PROG_ROM_ADD
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PROG_ROM_WORDS
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PROG_ROM_WORDS
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RAM_ADD
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RAM_ADD
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RAM_WORDS
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RAM_WORDS
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RESET_SENSE
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RESET_SENSE
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ROM_ADD
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ROM_ADD
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ROM_WORDS
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ROM_WORDS
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UART_DIV
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UART_DIV
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UART_PRESCALE
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UART_PRESCALE
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UART_PRE_SIZE
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UART_PRE_SIZE
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VEC_TABLE
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VEC_TABLE
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