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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 50... Line 50...
  none
  none
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      configuration
 
      default
 
    
 
    
 
      destination
      destination
      top.T6502_tb
      Nexys2_T6502_default_tb
    
 
    
 
      dest_dir
 
      ../verilog
 
    
 
    
 
      top
 
    
    
  
  
 
 
 
 
 
 
Line 192... Line 181...
    
    
      fs-sim
      fs-sim
 
 
      
      
        
        
        ../verilog/common/top.T6502_tb
        ../verilog/common/Nexys2_T6502_default_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
    
    
 
 
 
 
    
 
      fs-lint
 
 
 
      
 
        
 
        ../verilog/common/top.T6502_tb
 
        verilogSourcemodule
 
      
 
 
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
 
 

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