URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [rtl/] [xml/] [io_module_def.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 1...	Line 1...


`// //`	`// //`
`// Author : John Eaton Ouabache Designworks //`	`// Author : John Eaton Ouabache Designworks //`
`// //`	`// //`
`// Copyright (C) 2010 Authors and OPENCORES.ORG //`	`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
Line 84...	Line 84...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`configuration`
`default`


`dest_dir`
`io_ports`








`gen_registers`	`gen_registers`
`102.1`	`102.1`
`common`	`common`
Line 134...	Line 114...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`io_module_def`


`dest_dir`
`../verilog`





Line 167...	Line 143...

`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/io_module_def`
`verilogSourcemodule`	`verilogSourcemodule`





	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`







`fs-syn`	`fs-syn`




`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/io_module_def`
`verilogSourcemodule`	`verilogSourcemodule`




	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`