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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_module/] [sim/] [testbenches/] [xml/] [io_module_def_tb.xml] - Diff between revs 133 and 134

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Rev 133 Rev 134
Line 41... Line 41...
 
 
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      configuration
 
      default
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      configuration
 
      default
 
    
 
    
 
      destination
      destination
      top.tb
      io_module_def_tb
    
 
    
 
      dest_dir
 
      ../verilog
 
    
 
    
 
      top
 
    
    
  
  
 
 
 
 
 
 
Line 236... Line 206...
      fs-sim
      fs-sim
 
 
 
 
      
      
        
        
        ../verilog/common/top.tb
        ../verilog/common/io_module_def_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
 
 
Line 250... Line 220...
      fs-lint
      fs-lint
 
 
 
 
      
      
        
        
        ../verilog/common/top.tb
        ../verilog/common/io_module_def_tb
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
   
   

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