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https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version rxtx //
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// ./tools/verilog/gen_tb -vendor opencores.org -library io -component io_uart -version rxtx //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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io
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io
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io_uart
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io_uart
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rxtx_duth.design
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rxtx_duth.design
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addr
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addr
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clk
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clk
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cs
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cs
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cts_pad_in
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cts_pad_in
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enable
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enable
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rd
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rd
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rdata
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rdata
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reset
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reset
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rts_pad_out
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rts_pad_out
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rx_irq
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rx_irq
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rxd_data_avail_IRQ
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tx_irq
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tx_irq
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uart_rxd_pad_in
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txd_buffer_empty_NIRQ
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uart_txd_pad_out
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uart_rxd_pad_in
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wdata
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uart_txd_pad_out
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wr
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wdata
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wr
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dut
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dut
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