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/**********************************************************************/
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/* */
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/* ------- */
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/* / SOC \ */
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/* / GEN \ */
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/* / COMPONENT \ */
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/* ============== */
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/* | | */
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/* |____________| */
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/* */
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/* */
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/* Author(s): */
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/* - John Eaton, jt_eaton@opencores.org */
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/* */
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/**********************************************************************/
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/* */
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/* Copyright (C) <2010> */
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/* */
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/* This source file may be used and distributed without */
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/* restriction provided that this copyright statement is not */
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/* removed from the file and that any derivative work contains */
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/* the original copyright notice and the associated disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it */
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/* and/or modify it under the terms of the GNU Lesser General */
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/* Public License as published by the Free Software Foundation; */
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/* either version 2.1 of the License, or (at your option) any */
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/* later version. */
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/* */
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/* This source is distributed in the hope that it will be */
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/* useful, but WITHOUT ANY WARRANTY; without even the implied */
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/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
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/* PURPOSE. See the GNU Lesser General Public License for more */
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/* details. */
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/* */
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/* You should have received a copy of the GNU Lesser General */
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/* Public License along with this source; if not, download it */
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/* from http://www.opencores.org/lgpl.shtml */
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/* */
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/**********************************************************************/
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// display io controller for digilent Basys fpga board
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reg [3:0] divide;
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reg [3:0] divide;
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reg [3:0] number;
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reg [3:0] number;
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wire one_usec;
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always@(posedge clk ) led_pad_out <= PosL;
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always@(posedge clk ) led_pad_out <= PosL;
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always@(posedge clk ) PosS <= sw_pad_in;
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always@(posedge clk ) PosS <= sw_pad_in;
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always@(posedge clk ) PosB <= btn_pad_in;
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always@(posedge clk ) PosB <= btn_pad_in;
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cde_divider_def
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#(.SIZE(6))
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cde_divider(
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.divider_in (6'b100000),
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.divider_out (one_usec)
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);
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always@(posedge clk)
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always@(posedge clk)
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if(reset) divide <= 4'b0000;
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if(reset) divide <= 4'b0000;
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else
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else
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