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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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flash_memcontrl
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flash_memcontrl
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def default
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def
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slave_clk
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slave_clk
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clk
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clk
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clk
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clk
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slave_reset
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reset
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reset
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slave_reset
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gen_verilog
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104.0
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none
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common
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./tools/verilog/gen_verilog
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destination
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flash_memcontrl_def
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reset
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reset
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Hierarchical
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spirit:library="logic"
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spirit:name="flash_memcontrl"
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spirit:version="def.design"/>
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gen_verilog
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104.0
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none
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:*common:*
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tools/verilog/gen_verilog
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destination
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flash_memcontrl_def
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verilog
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="verilog"/>
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commoncommon
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Verilog
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Hierarchical
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fs-common
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-sim
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Hierarchical
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Hierarchical
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verilog
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="verilog"/>
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doc
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spirit:library="Testbench"
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spirit:name="toolflow"
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spirit:version="documentation"/>
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:*Documentation:*
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Verilog
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common:*common:*
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Verilog
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fs-common
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ADDR_BITS24
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sim:*Simulation:*
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Verilog
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fs-sim
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syn:*Synthesis:*
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Verilog
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fs-sim
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addr
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wire
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in
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ADDR_BITS-11
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wdata
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wire
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in
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150
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cs
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wire
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doc
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in
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10
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ipxact:library="Testbench"
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ipxact:name="toolflow"
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ipxact:version="documentation"/>
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:*Documentation:*
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Verilog
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rd
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wire
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in
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wr
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wire
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in
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stb
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wire
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in
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ub
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wire
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in
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lb
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wire
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in
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wait_out
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reg
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out
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rdata
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wire
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out
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150
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memadr_out
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reg
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out
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ADDR_BITS-11
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memdb_out
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reg
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out
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150
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memdb_oe
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addr
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reg
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wire
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out
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in
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ADDR_BITS-11
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memdb_in
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wdata
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wire
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wire
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in
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in
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150
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150
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memoe_n_out
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cs
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reg
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wire
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out
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in
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10
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memwr_n_out
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rd
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reg
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wire
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out
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in
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ramadv_n_out
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wr
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reg
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wire
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out
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in
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ramclk_out
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stb
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reg
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wire
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out
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in
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ramub_n_out
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ub
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reg
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wire
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out
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in
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ramlb_n_out
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lb
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reg
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wire
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out
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in
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ramcs_n_out
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wait_out
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reg
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reg
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out
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out
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ramcre_out
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rdata
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reg
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wire
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out
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out
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150
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ramwait_in
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memadr_out
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wire
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reg
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in
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out
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ADDR_BITS-11
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flashcs_n_out
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memdb_out
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reg
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reg
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out
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out
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150
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flashrp_n_out
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memdb_oe
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reg
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reg
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out
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out
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flashststs_in
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memdb_in
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wire
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wire
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in
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in
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150
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memoe_n_out
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reg
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out
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memwr_n_out
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reg
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out
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ramadv_n_out
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reg
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out
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ramclk_out
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reg
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out
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ramub_n_out
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reg
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out
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ramlb_n_out
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reg
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out
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ramcs_n_out
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fs-common
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reg
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out
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ramcre_out
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reg
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../verilog/top.body
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out
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verilogSourcefragment
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ramwait_in
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wire
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in
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flashcs_n_out
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reg
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out
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flashrp_n_out
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fs-sim
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reg
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out
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flashststs_in
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wire
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../verilog/copyright
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in
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verilogSourceinclude
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../verilog/common/flash_memcontrl_def
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verilogSourcemodule
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fs-syn
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../verilog/copyright
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verilogSourceinclude
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fs-common
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../verilog/common/flash_memcontrl_def
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verilogSourcemodule
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../verilog/top.body
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verilogSourcefragment
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fs-sim
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/flash_memcontrl_def
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verilogSourcemodule
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fs-syn
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../verilog/copyright
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verilogSourceinclude
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../verilog/common/flash_memcontrl_def
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verilogSourcemodule
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