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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [flash_memcontrl/] [sim/] [testbenches/] [verilog/] [tb.ext] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 1...	Line 1...


`assign stb =\|cs;`	`assign stb =\|cs;`

`wire [15:0] memdb_io;`	`wire [15:0] memdb_io;`
`wire addr_0;`
`micro_bus16_model_def`
`bus16`
`(`
`.clk ( clk ),`
`.reset ( reset ),`
`.addr ( {addr,addr_0} ),`
`.wdata ( wdata ),`
`.cs ( cs ),`
`.rd ( rd ),`
`.wr ( wr ),`
`.ub ( ub ),`
`.lb ( lb ),`
`.rdata ( rdata )`
`);`

	`assign addr = Addr[24:1];`



`cde_pad_se_dig #(.WIDTH(16))`	`cde_pad_se_dig #(.WIDTH(16))`
`memdb_buff`	`memdb_buff`
Line 30...	Line 16...
`.pad_in ( memdb_in ),`	`.pad_in ( memdb_in ),`
`.PAD ( memdb_io )`	`.PAD ( memdb_io )`
`);`	`);`


`pullup pu_ramwait ( ramwait_n );`	`pullup pu_ramwait ( ramwait_in );`

`mt45w8mw12_def`	`mt45w8mw12_def`
`psram (`	`psram (`
`.clk ( ramclk_out ),`	`.clk ( ramclk_out ),`
`.adv_n ( ramadv_n_out ),`	`.adv_n ( ramadv_n_out ),`
`.cre ( ramcre_out ),`	`.cre ( ramcre_out ),`
`.o_wait ( ramwait_n ),`	`.o_wait ( ramwait_in ),`
`.ce_n ( ramcs_n_out ),`	`.ce_n ( ramcs_n_out ),`
`.oe_n ( memoe_n_out ),`	`.oe_n ( memoe_n_out ),`
`.we_n ( memwr_n_out ),`	`.we_n ( memwr_n_out ),`
`.lb_n ( ramlb_n_out ),`	`.lb_n ( ramlb_n_out ),`
`.ub_n ( ramub_n_out ),`	`.ub_n ( ramub_n_out ),`

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