URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Show entire file |
Details |
Blame |
View Log
Rev 133 |
Rev 134 |
Line 1... |
Line 1... |
|
|
|
|
assign stb =|cs;
|
assign stb =|cs;
|
|
|
wire [15:0] memdb_io;
|
|
|
|
assign addr = Addr[24:1];
|
assign addr = Addr[24:1];
|
|
|
|
|
|
|
cde_pad_se_dig #(.WIDTH(16))
|
|
memdb_buff
|
|
(
|
|
.pad_out ( memdb_out ),
|
|
.pad_oe ( memdb_oe ),
|
|
.pad_in ( memdb_in ),
|
|
.PAD ( memdb_io )
|
|
);
|
|
|
|
|
|
pullup pu_ramwait ( ramwait_in );
|
pullup pu_ramwait ( ramwait_in );
|
|
|
mt45w8mw12_def
|
|
psram (
|
|
.clk ( ramclk_out ),
|
|
.adv_n ( ramadv_n_out ),
|
|
.cre ( ramcre_out ),
|
|
.o_wait ( ramwait_in ),
|
|
.ce_n ( ramcs_n_out ),
|
|
.oe_n ( memoe_n_out ),
|
|
.we_n ( memwr_n_out ),
|
|
.lb_n ( ramlb_n_out ),
|
|
.ub_n ( ramub_n_out ),
|
|
.addr ( memadr_out ),
|
|
.dq ( memdb_io )
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
assign STOP = 1'b0;
|
assign STOP = 1'b0;
|
assign BAD = 1'b0;
|
assign BAD = 1'b0;
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.