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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body.exp6] - Diff between revs 131 and 133

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Rev 131 Rev 133
Line 29... Line 29... 
assign mas_2_wdata_out = wdata_in;
 
assign mas_2_wdata_out = wdata_in;
 
assign mas_3_wdata_out = wdata_in;
 
assign mas_3_wdata_out = wdata_in;
 
assign mas_4_wdata_out = wdata_in;
 
assign mas_4_wdata_out = wdata_in;
 
assign mas_5_wdata_out = wdata_in;
 
assign mas_5_wdata_out = wdata_in;
 
 
 
 
 
assign mas_0_addr_out  = addr_in[7:0];
 
assign mas_0_addr_out  = addr_in[3:0];
 
assign mas_1_addr_out  = addr_in[7:0];
 
assign mas_1_addr_out  = addr_in[3:0];
 
assign mas_2_addr_out  = addr_in[7:0];
 
assign mas_2_addr_out  = addr_in[3:0];
 
assign mas_3_addr_out  = addr_in[7:0];
 
assign mas_3_addr_out  = addr_in[3:0];
 
assign mas_4_addr_out  = addr_in[7:0];
 
assign mas_4_addr_out  = addr_in[3:0];
 
assign mas_5_addr_out  = addr_in[7:0];
 
assign mas_5_addr_out  = addr_in[3:0];
 
 
 
 
 
assign  mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in;
 
assign  mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in;
 
assign  mas_1_cs_out = (addr_in[7:4] == 4'h1) && cs_in;
 
assign  mas_1_cs_out = (addr_in[7:4] == 4'h1) && cs_in;
 
assign  mas_2_cs_out = (addr_in[7:4] == 4'h2) && cs_in;
 
assign  mas_2_cs_out = (addr_in[7:4] == 4'h2) && cs_in;
 
assign  mas_3_cs_out = (addr_in[7:4] == 4'h3) && cs_in;
 
assign  mas_3_cs_out = (addr_in[7:4] == 4'h3) && cs_in;

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