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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 127...	Line 127...


`addr`	`addr`

`mas_0_addr_out`	`mas_0_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 188...	Line 188...


`addr`	`addr`

`mas_1_addr_out`	`mas_1_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 251...	Line 251...


`addr`	`addr`

`mas_2_addr_out`	`mas_2_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 310...	Line 310...


`addr`	`addr`

`mas_3_addr_out`	`mas_3_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 371...	Line 371...


`addr`	`addr`

`mas_4_addr_out`	`mas_4_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 427...	Line 427...






	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`configuration`
	`exp_default`


	`dest_dir`
	`io_ports`






`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
Line 590...	Line 605...






`SLA_ADDR_WIDTH8`
`SLA_DATA_WIDTH16`
`MAS_ADDR_WIDTH4`
`MAS_DATA_WIDTH8`






`clk`	`clk`
`wire`	`wire`
`in`	`in`

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