OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp5.xml] - Diff between revs 133 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 133 Rev 134
Line 428... Line 428...
 
 
 
 
 
 
 
 
 
 
  elab_verilog
 
  102.1
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/elab_verilog
 
    
 
    
 
      configuration
 
      exp_default
 
    
 
    
 
      dest_dir
 
      io_ports
 
    
 
  
 
 
 
 
 
 
 
 
 
  gen_verilog
  gen_verilog
  104.0
  104.0
  none
  none
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
      destination
      destination
      top.exp5
      micro_bus_exp5
    
 
    
 
      dest_dir
 
      ../verilog
 
    
    
  
  
 
 
 
 
 
 
Line 494... Line 471...
      
      
 
 
 
 
      
      
        
        
        ../verilog/common/top.exp5
        ../verilog/common/micro_bus_exp5
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
    
    
Line 517... Line 494...
 
 
 
 
 
 
      
      
        
        
        ../verilog/common/top.exp5
        ../verilog/common/micro_bus_exp5
        verilogSourcemodule
        verilogSourcemodule
      
      
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.