| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
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-->
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-->
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|
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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|
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opencores.org
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opencores.org
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logic
|
logic
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micro_bus
|
micro_bus
|
exp9 default
|
exp9
|
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mb_out
|
mb_out
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addr
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addr_in
|
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70
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rdata
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rdata_out
|
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150
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wdata
|
addr
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wdata_in
|
addr_in
|
70
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70
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rd
|
rdata
|
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rd_in
|
rdata_out
|
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150
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wr
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wdata
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wr_in
|
wdata_in
|
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70
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cs
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rd
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cs_in
|
rd_in
|
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wait
|
wr
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wait_out
|
wr_in
|
reg
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cs
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cs_in
|
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wait
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wait_out
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reg
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mas_0
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addr
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mas_0_addr_out
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30
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rdata
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mas_0_rdata_in
|
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70
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wdata
|
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mas_0_wdata_out
|
|
70
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rd
|
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mas_0_rd_out
|
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wr
|
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mas_0_wr_out
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cs
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mas_0_cs_out
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mas_0
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mas_1
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addr
|
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mas_0_addr_out
|
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30
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|
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|
addr
|
rdata
|
|
|
mas_1_addr_out
|
mas_0_rdata_in
|
30
|
70
|
|
|
|
|
|
|
|
|
rdata
|
wdata
|
|
|
mas_1_rdata_in
|
mas_0_wdata_out
|
70
|
70
|
|
|
|
|
|
|
|
|
wdata
|
rd
|
|
|
mas_1_wdata_out
|
mas_0_rd_out
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
wr
|
|
|
mas_1_rd_out
|
mas_0_wr_out
|
|
|
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|
|
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|
wr
|
cs
|
|
|
mas_1_wr_out
|
mas_0_cs_out
|
|
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cs
|
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mas_1_cs_out
|
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mas_2
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|
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addr
|
|
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|
mas_2_addr_out
|
|
30
|
|
|
|
|
|
|
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rdata
|
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|
mas_2_rdata_in
|
|
70
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|
|
|
|
|
|
|
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|
wdata
|
|
|
|
mas_2_wdata_out
|
|
70
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|
|
|
|
|
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|
mas_1
|
rd
|
|
|
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mas_2_rd_out
|
|
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|
wr
|
|
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mas_2_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
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mas_2_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_1_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_1_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_1_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
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|
mas_1_rd_out
|
|
|
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|
mas_3
|
|
|
wr
|
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mas_1_wr_out
|
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|
cs
|
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mas_1_cs_out
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_3_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_3_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_3_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_3_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_3_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_3_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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mas_2
|
addr
|
|
|
|
mas_4_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_4_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_4_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_4_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_4_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_4_cs_out
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_2_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_2_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_2_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_2_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_2_wr_out
|
|
|
|
|
|
|
mas_5
|
|
|
cs
|
|
|
|
mas_2_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_5_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_5_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_5_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_5_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_5_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_5_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_3
|
|
|
|
|
mas_6
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_6_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_6_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
addr
|
|
|
mas_6_wdata_out
|
mas_3_addr_out
|
70
|
30
|
|
|
|
|
|
|
|
|
rd
|
rdata
|
|
|
mas_6_rd_out
|
mas_3_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
wr
|
wdata
|
|
|
mas_6_wr_out
|
mas_3_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
cs
|
rd
|
|
|
mas_6_cs_out
|
mas_3_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_3_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_3_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_7
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_7_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_7_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_7_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_7_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_7_wr_out
|
|
|
|
|
|
|
|
|
mas_4
|
cs
|
|
|
|
mas_7_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_4_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
addr
|
rdata
|
|
|
mas_8_addr_out
|
mas_4_rdata_in
|
30
|
70
|
|
|
|
|
|
|
|
|
rdata
|
wdata
|
|
|
mas_8_rdata_in
|
mas_4_wdata_out
|
70
|
70
|
|
|
|
|
|
|
|
|
wdata
|
rd
|
|
|
mas_8_wdata_out
|
mas_4_rd_out
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
wr
|
|
|
mas_8_rd_out
|
mas_4_wr_out
|
|
|
|
|
|
|
|
|
wr
|
cs
|
|
|
mas_8_wr_out
|
mas_4_cs_out
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_8_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_5
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_5_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_5_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_5_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_5_rd_out
|
|
|
|
|
|
|
|
|
gen_verilog
|
wr
|
104.0
|
|
none
|
mas_5_wr_out
|
common
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
micro_bus_exp9
|
|
|
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_5_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
../verilog/top.body.exp9
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/micro_bus_exp9
|
|
verilogSourcemodule
|
|
|
|
|
|
|
mas_6
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
addr
|
|
|
|
mas_6_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
mas_6_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_6_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_6_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
../verilog/common/micro_bus_exp9
|
|
verilogSourcemodule
|
mas_6_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_6_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_7
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_7_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_7_rdata_in
|
|
70
|
|
|
|
|
|
|
|
|
|
wdata
|
|
|
|
mas_7_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
commoncommon
|
rd
|
|
|
|
mas_7_rd_out
|
|
|
|
|
|
|
Verilog
|
|
|
wr
|
|
|
fs-common
|
mas_7_wr_out
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
cs
|
|
|
|
mas_7_cs_out
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_8
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
addr
|
|
|
|
mas_8_addr_out
|
|
30
|
|
|
|
|
|
|
|
|
|
rdata
|
|
|
|
mas_8_rdata_in
|
|
70
|
|
|
|
|
|
|
enable
|
|
wire
|
wdata
|
in
|
|
|
mas_8_wdata_out
|
|
70
|
|
|
|
|
|
|
|
|
|
rd
|
|
|
|
mas_8_rd_out
|
|
|
|
|
|
|
|
|
|
wr
|
|
|
|
mas_8_wr_out
|
|
|
|
|
|
|
|
|
|
cs
|
|
|
|
mas_8_cs_out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4
|
|
mb_out
|
|
|
|
|
|
|
|
|
|
mas_0
|
|
0x00
|
|
|
|
|
|
|
|
|
|
mas_1
|
|
0x10
|
|
|
|
|
|
|
|
|
|
mas_2
|
|
0x20
|
|
|
|
|
|
|
|
|
|
mas_3
|
|
0x30
|
|
|
|
|
|
|
|
mas_4
|
|
0x40
|
|
|
|
|
|
|
|
|
|
mas_5
|
|
0x50
|
|
|
|
|
|
|
|
|
|
|
|
mas_6
|
|
0x60
|
|
|
|
|
|
|
|
|
|
mas_7
|
|
0x70
|
|
|
|
|
|
|
|
|
|
mas_8
|
|
0x80
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
|
104.0
|
|
none
|
|
:*common:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
micro_bus_exp9
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_0
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_1
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_2
|
fs-common
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_3
|
|
0x10
|
../verilog/top.body.exp9
|
8
|
verilogSourcefragment
|
|
|
|
|
|
|
mas_4
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_5
|
fs-sim
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_6
|
|
0x10
|
../verilog/copyright.v
|
8
|
verilogSourceinclude
|
|
|
|
|
|
|
mas_7
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_8
|
|
0x10
|
../verilog/common/micro_bus_exp9
|
8
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright.v
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
|
|
|
|
../verilog/common/micro_bus_exp9
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
common:*common:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-common
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
reset
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
enable
|
|
wire
|
|
in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4
|
|
mb_out
|
|
|
|
|
|
|
|
mas_0
|
|
0x00
|
|
|
|
|
|
|
|
|
|
mas_1
|
|
0x10
|
|
|
|
|
|
|
|
|
|
mas_2
|
|
0x20
|
|
|
|
|
|
|
|
|
|
mas_3
|
|
0x30
|
|
|
|
|
|
|
|
mas_4
|
|
0x40
|
|
|
|
|
|
|
|
|
|
mas_5
|
|
0x50
|
|
|
|
|
|
|
|
|
|
mas_6
|
|
0x60
|
|
|
|
|
|
|
|
|
|
mas_7
|
|
0x70
|
|
|
|
|
|
|
|
|
|
mas_8
|
|
0x80
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mas_0
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_1
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_2
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_3
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_4
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_5
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_6
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_7
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
mas_8
|
|
0x10
|
|
8
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
