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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_exp9.xml] - Diff between revs 131 and 133

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Rev 131	Rev 133
Line 131...	Line 131...


`addr`	`addr`

`mas_0_addr_out`	`mas_0_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 192...	Line 192...


`addr`	`addr`

`mas_1_addr_out`	`mas_1_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 255...	Line 255...


`addr`	`addr`

`mas_2_addr_out`	`mas_2_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 314...	Line 314...


`addr`	`addr`

`mas_3_addr_out`	`mas_3_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 375...	Line 375...


`addr`	`addr`

`mas_4_addr_out`	`mas_4_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 434...	Line 434...


`addr`	`addr`

`mas_5_addr_out`	`mas_5_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 494...	Line 494...


`addr`	`addr`

`mas_6_addr_out`	`mas_6_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 555...	Line 555...


`addr`	`addr`

`mas_7_addr_out`	`mas_7_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 615...	Line 615...


`addr`	`addr`

`mas_8_addr_out`	`mas_8_addr_out`
`70`	`30`




`rdata`	`rdata`
Line 676...	Line 676...






	`elab_verilog`
	`102.1`
	`none`
	`:Simulation:`
	`./tools/verilog/elab_verilog`


	`configuration`
	`exp_default`


	`dest_dir`
	`io_ports`








Line 840...	Line 857...






`SLA_ADDR_WIDTH8`
`SLA_DATA_WIDTH16`
`MAS_ADDR_WIDTH4`
`MAS_DATA_WIDTH8`






`clk`	`clk`
`wire`	`wire`

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