URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component micro_bus -version def //
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// ./tools/verilog/gen_tb -vendor opencores.org -library logic -component micro_bus -version def //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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micro_bus
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micro_bus
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def_duth.design
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def_duth.design
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addr_in
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addr_in
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clk
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clk
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data_addr
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data_addr
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data_be
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data_be
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data_cs
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data_cs
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data_rd
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data_rd
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data_rdata
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data_rdata
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data_wdata
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data_wdata
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data_wr
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data_wr
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enable
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enable
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ext_mem_addr
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ext_mem_addr
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ext_mem_cs
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ext_mem_cs
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ext_mem_rd
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ext_mem_rd
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ext_mem_rdata
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ext_mem_rdata
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ext_mem_wait
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ext_mem_wait
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ext_mem_wdata
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ext_mem_wdata
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ext_mem_wr
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ext_mem_wr
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io_reg_addr
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io_reg_addr
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io_reg_cs
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io_reg_cs
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io_reg_rd
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io_reg_rd
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io_reg_rdata
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io_reg_rdata
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io_reg_wait
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io_reg_wait
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io_reg_wdata
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io_reg_wdata
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io_reg_wr
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io_reg_wr
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mem_addr
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mem_addr
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mem_cs
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mem_cs
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mem_rd
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mem_rd
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mem_rdata
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mem_rdata
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mem_wait
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mem_wait
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mem_wdata
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mem_wdata
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mem_wr
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mem_wr
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prog_rom_mem_addr
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prog_rom_mem_addr
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prog_rom_mem_cs
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prog_rom_mem_cs
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prog_rom_mem_rd
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prog_rom_mem_rd
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prog_rom_mem_rdata
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prog_rom_mem_rdata
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prog_rom_mem_wdata
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prog_rom_mem_wdata
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prog_rom_mem_wr
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prog_rom_mem_wr
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rd_in
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rd_in
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rdata_out
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rdata_out
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reset
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reset
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sh_prog_rom_mem_addr
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sh_prog_rom_mem_addr
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sh_prog_rom_mem_cs
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sh_prog_rom_mem_cs
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sh_prog_rom_mem_rd
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sh_prog_rom_mem_rd
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sh_prog_rom_mem_rdata
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sh_prog_rom_mem_rdata
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sh_prog_rom_mem_wdata
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sh_prog_rom_mem_wdata
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sh_prog_rom_mem_wr
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sh_prog_rom_mem_wr
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wdata_in
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wdata_in
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wr_in
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wr_in
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dut
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dut
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ADD
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ADD
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CH0_BITS
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CH0_BITS
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CH0_MATCH
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CH0_MATCH
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CH1_BITS
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CH1_BITS
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CH1_MATCH
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CH1_MATCH
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CH2_BITS
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CH2_BITS
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CH2_MATCH
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CH2_MATCH
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CH3_BITS
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CH3_BITS
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CH3_MATCH
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CH3_MATCH
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CH4_BITS
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CH4_BITS
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CH4_MATCH
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CH4_MATCH
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CH5_BITS
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CH5_BITS
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CH5_MATCH
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CH5_MATCH
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