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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Diff between revs 131 and 133

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Rev 131 Rev 133
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//                                                                        //
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
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  none
  none
  common
  common
  ./tools/verilog/gen_verilog
  ./tools/verilog/gen_verilog
    
    
    
    
 
      configuration
 
      default
 
    
 
    
      destination
      destination
      top.tb
      top.tb
    
    
    
    
      dest_dir
      dest_dir
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    ADDR_WIDTH16
    addr_width16
 
 
 
 
 
 
       
       
 
 

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