| Line 25... |
Line 25... |
// You should have received a copy of the GNU Lesser General //
|
// You should have received a copy of the GNU Lesser General //
|
// Public License along with this source; if not, download it //
|
// Public License along with this source; if not, download it //
|
// from http://www.opencores.org/lgpl.shtml //
|
// from http://www.opencores.org/lgpl.shtml //
|
// //
|
// //
|
-->
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
logic
|
logic
|
ps2_interface
|
ps2_interface
|
def default
|
def
|
|
|
|
|
|
|
|
|
slave_clk
|
slave_clk
|
|
|
|
|
|
|
|
|
|
|
clk
|
|
clk
|
clk
|
|
clk
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
slave_reset
|
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
|
|
|
|
|
slave_reset
|
|
|
|
|
|
|
|
|
|
|
|
|
|
reset
|
|
reset
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ps2
|
|
|
|
|
|
|
|
|
|
|
|
|
ps2
|
clk_pad_oe
|
|
ps2_clk_pad_oe
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clk_pad_in
|
clk_pad_oe
|
ps2_clk_pad_in
|
ps2_clk_pad_oe
|
|
|
|
|
|
|
|
|
data_pad_oe
|
clk_pad_in
|
ps2_data_pad_oe
|
ps2_clk_pad_in
|
|
|
|
|
|
|
|
|
data_pad_in
|
data_pad_oe
|
ps2_data_pad_in
|
ps2_data_pad_oe
|
|
|
|
|
|
|
|
|
|
data_pad_in
|
|
ps2_data_pad_in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_sim
|
|
104.0
|
|
none
|
|
:*Simulation:*
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
ps2_interface_def
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_syn
|
|
104.0
|
|
none
|
|
:*Synthesis:*
|
|
./tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
ps2_interface_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_sim
|
|
104.0
|
|
none
|
|
:*Simulation:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
ps2_interface_def
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog_syn
|
|
104.0
|
|
none
|
|
:*Synthesis:*
|
|
tools/verilog/gen_verilog
|
|
|
|
|
|
destination
|
|
ps2_interface_def
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Hierarchical
|
|
|
|
|
|
spirit:library="logic"
|
|
spirit:name="ps2_interface"
|
|
spirit:version="def.design"/>
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="verilog"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
Hierarchical
|
|
|
|
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
Hierarchical
|
|
Hierarchical
|
|
|
|
|
Verilog
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
verilog
|
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="verilog"/>
|
|
|
|
|
|
|
|
|
doc
|
|
|
|
|
|
spirit:library="Testbench"
|
|
spirit:name="toolflow"
|
|
spirit:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
|
|
busy
|
Verilog
|
wire
|
|
out
|
|
|
fs-sim
|
|
|
|
|
|
|
tx_data
|
|
wire
|
|
in
|
|
70
|
|
|
|
|
|
tx_write
|
|
wire
|
syn:*Synthesis:*
|
in
|
|
|
|
|
|
rx_data
|
Verilog
|
reg
|
|
out
|
|
70
|
fs-syn
|
|
|
|
|
|
|
rx_read
|
|
reg
|
|
out
|
|
|
|
|
|
rx_full
|
|
reg
|
doc
|
out
|
|
|
|
|
ipxact:library="Testbench"
|
|
ipxact:name="toolflow"
|
|
ipxact:version="documentation"/>
|
|
|
|
:*Documentation:*
|
|
Verilog
|
|
|
|
|
rx_parity_error
|
|
reg
|
|
out
|
|
|
|
|
|
rx_parity_rcv
|
|
reg
|
|
out
|
|
|
|
|
|
rx_parity_cal
|
|
reg
|
|
out
|
|
|
|
|
|
rx_frame_error
|
|
reg
|
|
out
|
|
|
|
|
|
rx_clear
|
busy
|
wire
|
wire
|
in
|
out
|
|
|
|
|
tx_buffer_empty
|
tx_data
|
wire
|
wire
|
out
|
in
|
|
70
|
|
|
|
|
tx_ack_error
|
tx_write
|
regx
|
wire
|
out
|
in
|
|
|
|
|
|
rx_data
|
|
reg
|
|
out
|
|
70
|
|
|
|
|
|
rx_read
|
|
reg
|
|
out
|
|
|
|
|
|
rx_full
|
|
reg
|
|
out
|
|
|
|
|
|
rx_parity_error
|
|
reg
|
|
out
|
|
|
|
|
|
rx_parity_rcv
|
|
reg
|
|
out
|
|
|
|
|
|
rx_parity_cal
|
|
reg
|
|
out
|
|
|
|
|
|
rx_frame_error
|
fs-sim
|
reg
|
|
out
|
|
|
|
|
|
rx_clear
|
|
wire
|
../verilog/copyright
|
in
|
verilogSourceinclude
|
|
|
|
|
|
|
tx_buffer_empty
|
|
wire
|
../verilog/sim/ps2_interface_def
|
out
|
verilogSourcemodule
|
|
|
|
|
|
|
tx_ack_error
|
fsm
|
regx
|
../verilog/fsm
|
out
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
../verilog/top.sim
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
fs-sim
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/sim/ps2_interface_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
fs-syn
|
fsm
|
|
../verilog/fsm
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
../verilog/copyright
|
../verilog/top.body
|
verilogSourceinclude
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
../verilog/syn/ps2_interface_def
|
../verilog/top.sim
|
verilogSourcemodule
|
verilogSourcefragment
|
|
|
|
|
|
|
fsm
|
|
../verilog/fsm
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/sim/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
|
|
|
|
|
|
|
../verilog/copyright
|
|
verilogSourceinclude
|
|
|
|
|
|
|
|
|
|
../verilog/syn/ps2_interface_def
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
fsm
|
|
../verilog/fsm
|
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
|
../verilog/top.body
|
|
verilogSourcefragment
|
|
|
|
|
|
|
|
dest_dir
|
|
../views/syn/
|
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
