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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Diff between revs 133 and 134

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Rev 133	Rev 134
Line 115...	Line 115...








`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`











`gen_verilog_sim`	`gen_verilog_sim`
`104.0`	`104.0`
`none`	`none`
`:Simulation:`	`:Simulation:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.sim`	`ps2_interface_def`


`dest_dir`
`../verilog`





Line 164...	Line 138...
`:Synthesis:`	`:Synthesis:`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.out.syn`	`ps2_interface_def`


`dest_dir`
`../verilog`













`fs-sim`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/sim/top.out.sim`
`verilogSourcemodule`



`fsm`
`../verilog/fsm`
`verilogSourcemodule`




`../verilog/top.body`
`verilogSourcefragment`




`../verilog/top.sim`
`verilogSourcefragment`







`fs-syn`



`../verilog/copyright.v`
`verilogSourceinclude`




`../verilog/syn/top.out.syn`
`verilogSourcemodule`



`fsm`
`../verilog/fsm`
`verilogSourcemodule`




`../verilog/top.body`
`verilogSourcefragment`














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`FREQ24`
`CLK_HOLD_DELAY100`
`DATA_SETUP_DELAY20`
`DEBOUNCE_DELAY4'b1111`





`busy`	`busy`
`wire`	`wire`
`out`	`out`
Line 409...	Line 293...








	`fs-sim`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/sim/ps2_interface_def`
	`verilogSourcemodule`



	`fsm`
	`../verilog/fsm`
	`verilogSourcemodule`




	`../verilog/top.body`
	`verilogSourcefragment`




	`../verilog/top.sim`
	`verilogSourcefragment`






	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`







	`fs-syn`



	`../verilog/copyright`
	`verilogSourceinclude`




	`../verilog/syn/ps2_interface_def`
	`verilogSourcemodule`



	`fsm`
	`../verilog/fsm`
	`verilogSourcemodule`




	`../verilog/top.body`
	`verilogSourcefragment`



	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Diff between revs 133 and 134