URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 1...	Line 1...


`// //`	`// //`
`// Author : John Eaton Ouabache Designworks //`	`// Author : John Eaton Ouabache Designworks //`
`// //`	`// //`
`// Copyright (C) 2010 Authors and OPENCORES.ORG //`	`// Copyright (C) 2010 Authors and OPENCORES.ORG //`
Line 72...	Line 72...








`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_verilog`	`gen_verilog`
`104.0`	`104.0`
`none`	`none`
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top`	`serial_rcvr_def`


`dest_dir`
`../verilog`





Line 139...	Line 116...

`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/serial_rcvr_def`
`verilogSourcemodule`	`verilogSourcemodule`




	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`










`fs-syn`	`fs-syn`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top`	`../verilog/common/serial_rcvr_def`
`verilogSourcemodule`	`verilogSourcemodule`



	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`







Line 238...	Line 230...









`doc`	`doc`


`spirit:library="Testbench"`	`spirit:library="Testbench"`