URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_fifo.xml] - Diff between revs 133 and 134

Rev 133	Rev 134
Line 74...	Line 74...






`elab_verilog`
`102.1`
`none`
`:Simulation:`
`./tools/verilog/elab_verilog`


`dest_dir`
`io_ports`








`gen_verilog`	`gen_verilog`
Line 100...	Line 86...
`common`	`common`
`./tools/verilog/gen_verilog`	`./tools/verilog/gen_verilog`


`destination`	`destination`
`top.fifo`	`serial_rcvr_fifo`


`dest_dir`
`../verilog`





Line 149...	Line 131...

`fs-sim`	`fs-sim`



`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top.fifo`	`../verilog/common/serial_rcvr_fifo`
`verilogSourcemodule`	`verilogSourcemodule`



	`dest_dir`
	`../views/sim/`
	`verilogSourcelibraryDir`







Line 170...	Line 158...
`fs-syn`	`fs-syn`




`../verilog/copyright.v`	`../verilog/copyright`
`verilogSourceinclude`	`verilogSourceinclude`




`../verilog/common/top.fifo`	`../verilog/common/serial_rcvr_fifo`
`verilogSourcemodule`	`verilogSourcemodule`



	`dest_dir`
	`../views/syn/`
	`verilogSourcelibraryDir`







Line 268...	Line 262...






`WIDTH8`
`SIZE4`
`SAMPLE4'b0111`
`START_VALUE1'b0`
`STOP_VALUE1'b1`
`RX_FIFO_SIZE4`
`RX_FIFO_WORDS16`





`edge_enable`	`edge_enable`