URL
https://opencores.org/ocsvn/socgen/socgen/trunk
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// Generated File Do Not EDIT //
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// Generated File Do Not EDIT //
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// //
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// //
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// regen by adding -tb to gen_verilog script //
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// regen by adding -tb to gen_verilog script //
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// //
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// //
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-->
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-->
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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opencores.org
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logic
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logic
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serial_rcvr
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serial_rcvr
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bfm.design
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bfm.design
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xmit_edge_enable
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xmit_edge_enable
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reg
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reg
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xmit_parity_enable
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xmit_parity_enable
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reg
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reg
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xmit_parity_type
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xmit_parity_type
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reg
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reg
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xmit_parity_force
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xmit_parity_force
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reg
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reg
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xmit_load
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xmit_load
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reg
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reg
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xmit_start_value
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xmit_start_value
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reg
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reg
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xmit_stop_value
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xmit_stop_value
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reg
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reg
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xmit_data
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xmit_data
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reg
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reg
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WIDTH-10
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WIDTH-10
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shift_buffer
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shift_buffer
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wire
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wire
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WIDTH-10
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WIDTH-10
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clk
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clk
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reset
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reset
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xmit_edge_enable
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xmit_edge_enable
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xmit_parity_enable
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xmit_parity_enable
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xmit_parity_type
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xmit_parity_type
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xmit_parity_force
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xmit_parity_force
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xmit_load
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xmit_load
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xmit_start_value
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xmit_start_value
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xmit_stop_value
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xmit_stop_value
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serial
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serial
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xmit_buffer_empty
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xmit_buffer_empty
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xmit_data
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xmit_data
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dutx
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dutx
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8
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8
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4
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4
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