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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [componentCfg.xml] - Diff between revs 131 and 134

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Rev 131	Rev 134
Line 27...	Line 27...








	`default`
	`def`

	`PRESCALE5'b01100`
	`PRE_SIZE5`
	`SIZE8`
	`DIV0`
	`DIV_SIZE4`






	`rxtx`
	`rxtx`

	`PRESCALE5'b01100`
	`PRE_SIZE5`
	`SIZE8`
	`DIV0`
	`DIV_SIZE4`
	`TX_FIFO_SIZE3`
	`TX_FIFO_WORDS8`
	`RX_FIFO_SIZE3`
	`RX_FIFO_WORDS8`





	`rx`
	`rx`

	`PRESCALE5'b01100`
	`PRE_SIZE5`
	`SIZE8`
	`DIV0`
	`DIV_SIZE4`
	`RX_FIFO_SIZE3`
	`RX_FIFO_WORDS8`




	`tx`
	`tx`

	`PRESCALE5'b01100`
	`PRE_SIZE5`
	`SIZE8`
	`DIV0`
	`DIV_SIZE4`
	`TX_FIFO_SIZE3`
	`TX_FIFO_WORDS8`













`uart/sim`	`uart/sim`

Line 42...	Line 110...




`uart_def_tb`	`uart_def_tb`
	`default`
`def_tb`	`def_tb`

`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`

Line 61...	Line 130...



`uart_rx_tb`	`uart_rx_tb`
`rx_tb`	`rx_tb`
	`rx`

`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`


Line 80...	Line 150...



`uart_tx_tb`	`uart_tx_tb`
`tx_tb`	`tx_tb`
	`tx`

`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`


Line 101...	Line 172...



`uart_rxtx_tb`	`uart_rxtx_tb`
`rxtx_tb`	`rxtx_tb`
	`rxtx`

`PERIOD40`	`PERIOD40`
`TIMEOUT100000`	`TIMEOUT100000`


Line 118...	Line 190...



`uart_def_lint`	`uart_def_lint`
`def_lint`	`def_lint`
	`default`

`rtl_check`	`rtl_check`





`uart_rx_lint`	`uart_rx_lint`
`rx_lint`	`rx_lint`
	`rx`

`rtl_check`	`rtl_check`






`uart_tx_lint`	`uart_tx_lint`
`tx_lint`	`tx_lint`
	`tx`

`rtl_check`	`rtl_check`





`uart_rxtx_lint`	`uart_rxtx_lint`
`rxtx_lint`	`rxtx_lint`
	`rxtx`

`rtl_check`	`rtl_check`

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