URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [verilog/] [top.body.tx] - Diff between revs 131 and 134

Rev 131	Rev 134
Line 12...	Line 12...






	`reg [DIV_SIZE-1:0] baud_divide_cnt;`
	`reg baud_divider_out;`

	`always@(posedge clk)`
	`if(reset) baud_divider_out <= 1'b1;`
	`else`
	`if(!baud_clk) baud_divider_out <= 1'b0;`
	`else baud_divider_out <= ( baud_divide_cnt == {DIV_SIZE{1'b0}} );`



	`always@(posedge clk)`
	`if(reset) baud_divide_cnt <= divider_in;`
	`else`
	`if(!baud_clk) baud_divide_cnt <= baud_divide_cnt;`
	`else`
	`if(!(\|baud_divide_cnt)) baud_divide_cnt <= divider_in;`
	`else baud_divide_cnt <= baud_divide_cnt - 'b1;`




`generate`	`generate`

`if(DIV == 0)`	`if(DIV == 0)`
`begin`	`begin`
`assign baud_clk_div = baud_clk;`	`assign baud_clk_div = baud_clk;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`cde_divider_def`
`#(.SIZE(DIV_SIZE))`	`assign baud_clk_div = baud_divider_out;`
`baud_divider (`
`.clk ( clk ),`
`.reset ( reset ),`
`.divider_in ( divider_in ),`
`.enable ( baud_clk ),`
`.divider_out ( baud_clk_div )`
`);`
`end`	`end`

`endgenerate`	`endgenerate`












`always@(posedge clk)`	`always@(posedge clk)`
`if(reset)`	`if(reset)`
`begin`	`begin`