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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Diff between revs 134 and 135

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Rev 134 Rev 135
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//   You should have received a copy of the GNU Lesser General            //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
//                                                                        //
-->
-->
 
 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
 
opencores.org
opencores.org
logic
logic
uart
uart
def  default
def
 
 
 
 
 
 
 slave_clk
 slave_clk
  
  
  
  
  
      
    
  
      
    
        clk
      
        clk
        clk
      
        clk
    
      
 
    
 
        
 
      
 
  
 
 
 
 
 
 
 slave_reset
 slave_reset
  
  
  
  
  
      
    
  
      
    
        reset
      
        reset
        reset
      
        reset
    
      
 
    
 
          
 
      
 
  
 
 
 
 
 
 
 
 
 
 
 uart
 uart
  
  
  
  
  
      
    
  
 
 
      
    
        txd_pad_out
 
        txd_pad_out
 
      
 
 
 
 
      
 
        txd_pad_out
 
        txd_pad_out
 
      
 
 
      
 
        rxd_pad_in
 
        rxd_pad_in
 
      
 
 
 
 
      
 
        rxd_pad_in
 
        rxd_pad_in
 
      
 
 
    
 
 
 
 
 
 
    
 
 
 rxd_data_avail
        
  
      
  
 
  
 
    
 
 
 
      
 
        IRQ
 
        rxd_data_avail_IRQ
 
      
 
 
 
    
  
 
 
 
 
 
 
 
 
 
 
 txd_buffer_empty
 
  
 
  
 
  
 
    
 
 
 
      
 
        NIRQ
 
        txd_buffer_empty_NIRQ
 
      
 
 
 
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog_sim
 
  104.0
 
  none
 
  :*Simulation:*
 
  tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      uart_def
 
    
 
  
 
 
 
 
 
 
 
 
 
  gen_verilog_syn
 
  104.0
 
  none
 
  :*Synthesis:*
 
  tools/verilog/gen_verilog
 
    
 
    
 
      destination
 
      uart_def
 
    
 
  
 
 
 
 
 
 
  gen_verilog_sim
 
  104.0
 
  none
 
  :*Simulation:*
 
  ./tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      uart_def
 
    
 
  
 
 
 
 
 
 
 
 
 
  gen_verilog_syn
 
  104.0
 
  none
 
  :*Synthesis:*
 
  ./tools/verilog/gen_verilog
 
    
 
    
 
      destination
 
      uart_def
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
    
 
      fs-sim
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
 
    
      
      fs-sim
        
 
        ../verilog/sim/uart_def
 
        verilogSourcemodule
 
      
 
 
      
      
        
        
        ../verilog/copyright.v
        ../verilog/top.body
        verilogSourceinclude
        verilogSourcefragment
      
      
 
 
 
      
 
        
 
        ../verilog/top.sim
 
        verilogSourcefragment
 
      
 
 
      
   
        
        dest_dir
        ../verilog/sim/uart_def
        ../views/sim/
        verilogSourcemodule
        verilogSourcelibraryDir
      
      
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
      
 
        
 
        ../verilog/top.sim
 
        verilogSourcefragment
 
      
 
 
 
   
 
        dest_dir
 
        ../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
    
 
 
 
 
 
 
    
    
 
      fs-syn
 
 
 
      
 
        
 
        ../verilog/copyright.v
 
        verilogSourceinclude
 
      
 
 
 
 
    
      
      fs-syn
        
 
        ../verilog/syn/uart_def
 
        verilogSourcemodule
 
      
 
 
      
      
        
        
        ../verilog/copyright.v
        ../verilog/top.body
        verilogSourceinclude
        verilogSourcefragment
      
      
 
 
 
 
      
   
        
        dest_dir
        ../verilog/syn/uart_def
        ../views/syn/
        verilogSourcemodule
        verilogSourcelibraryDir
      
      
 
 
      
 
        
 
        ../verilog/top.body
 
        verilogSourcefragment
 
      
 
 
 
 
 
   
    
        dest_dir
 
        ../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
                
       
                        
 
                                Hierarchical
 
                                
 
                        
 
                
 
 
              
 
              Hierarchical
 
 
 
              
 
                                   spirit:library="logic"
 
                                   spirit:name="uart"
 
                                   spirit:version="def.design"/>
 
              
 
 
 
 
 
              
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
 
 
  
 
 
 
              
 
              Hierarchical
 
                  Hierarchical
 
              
 
 
              
 
              sim:*Simulation:*
 
 
 
              Verilog
              
              
              verilog
                     
              
                            fs-sim
              
                     
                                   ipxact:library="Testbench"
              
                                   ipxact:name="toolflow"
 
                                   ipxact:version="verilog"/>
 
              
 
              
 
 
              
 
              syn:*Synthesis:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-syn
 
                     
 
              
 
 
 
 
 
              
 
              doc
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
              
 
              sim:*Simulation:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-sim
 
                     
 
              
 
 
      
              
 
              syn:*Synthesis:*
 
 
 
              Verilog
 
              
 
                     
 
                            fs-syn
 
                     
 
              
 
 
 
 
 
              
 
              doc
 
              
 
              
 
                                   ipxact:library="Testbench"
 
                                   ipxact:name="toolflow"
 
                                   ipxact:version="documentation"/>
 
              
 
              :*Documentation:*
 
              Verilog
 
              
 
 
 
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
parity_enable
 
wire
 
in
 
 
 
 
 
divider_in
 
wire
 
in
 
DIV_SIZE-10
 
 
 
 
 
cts_pad_in
 
wire
 
in
 
 
 
 
 
rts_pad_out
 
reg
 
out
 
 
 
 
 
 
 
cts_out
 
reg
 
out
 
 
 
 
 
rts_in
parity_enable
wire
wire
in
in
 
 
 
 
txd_parity
divider_in
wire
wire
in
in
 
DIV_SIZE-10
 
 
 
 
txd_force_parity
cts_pad_in
wire
wire
in
in
 
 
 
 
txd_load
rts_pad_out
wire
reg
in
out
 
 
 
 
txd_break
 
wire
 
in
 
 
 
 
 
txd_data_in
cts_out
wire
reg
in
out
SIZE-10
 
 
 
 
 
txd_buffer_empty
rts_in
wire
wire
out
in
 
 
 
 
rxd_data_avail_stb
txd_parity
wire
wire
in
in
 
 
 
 
rxd_data_avail
txd_force_parity
wire
wire
out
in
 
 
 
 
rxd_parity
txd_load
wire
wire
in
in
 
 
 
 
rxd_force_parity
txd_break
wire
wire
in
in
 
 
 
 
rxd_data_out
txd_data_in
wire
wire
out
in
SIZE-10
SIZE-10
 
 
 
 
rxd_parity_error
txd_buffer_empty
wire
wire
out
out
 
 
 
 
rxd_stop_error
rxd_data_avail_stb
wire
wire
out
in
 
 
 
 
 
rxd_data_avail
 
wire
 
out
 
 
 
 
 
rxd_parity
 
wire
 
in
 
 
 
 
 
rxd_force_parity
 
wire
 
in
 
 
 
 
 
rxd_data_out
 
wire
 
out
 
SIZE-10
 
 
 
 
 
rxd_parity_error
 
wire
 
out
 
 
 
 
 
rxd_stop_error
 
wire
 
out
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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